Seng-Sooi Lim

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit package
- Patent number 6,603,200
- Issue date Aug 5, 2003
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded integrated circuit package
- Patent number 6,525,421
- Issue date Feb 25, 2003
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overmold integrated circuit package
- Patent number 6,519,844
- Issue date Feb 18, 2003
- LSI Logic Corporation
- Kumar Nagarajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mechanically interlocking ball grid array packages and method of ma...
- Patent number 6,512,293
- Issue date Jan 28, 2003
- LSI Logic Corporation
- Chok J. Chia
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for programming a substrate for array-type packages
- Patent number 6,492,253
- Issue date Dec 10, 2002
- LSI Logic Corporation
- Chok J. Chia
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multiple layer tape ball grid array package
- Patent number 6,285,077
- Issue date Sep 4, 2001
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Grooved semiconductor die for flip-chip heat sink attachment
- Patent number 6,225,695
- Issue date May 1, 2001
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded array integrated circuit package
- Patent number 6,114,189
- Issue date Sep 5, 2000
- LSI Logic Corp.
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for packaging an integrated circuit using encapsu...
- Patent number 6,081,997
- Issue date Jul 4, 2000
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable substrate for array-type packages
- Patent number 6,054,767
- Issue date Apr 25, 2000
- LSI Logic Corp.
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple sized die
- Patent number 6,040,632
- Issue date Mar 21, 2000
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermally enhanced tape ball grid array package
- Patent number 6,002,169
- Issue date Dec 14, 1999
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for using a removeable plating bus layer for high density s...
- Patent number 5,981,311
- Issue date Nov 9, 1999
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for stackable molded lead frame ball grid arra...
- Patent number 5,973,393
- Issue date Oct 26, 1999
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and fabrication method which advantageously co...
- Patent number 5,973,397
- Issue date Oct 26, 1999
- LSI Logic Corporation
- Qwai H. Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overmolded package body on a substrate
- Patent number 5,927,505
- Issue date Jul 27, 1999
- LSI Logic Corporation
- Chok J. Chia
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Grant
Method of improving molding of an overmolded package body on a subs...
- Patent number 5,744,084
- Issue date Apr 28, 1998
- LSI Logic Corporation
- Chok J. Chia
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Grant
Process for manufacturing and mounting a semiconductor device leadf...
- Patent number 5,643,835
- Issue date Jul 1, 1997
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Partially-molded, PCB chip carrier package for certain non-square d...
- Patent number 5,594,626
- Issue date Jan 14, 1997
- LSI Logic Corporation
- Michael D. Rostoker
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of cooling a packaged electronic device
- Patent number 5,568,683
- Issue date Oct 29, 1996
- LSI Logic Corporation
- Chok J. Chia
- F02 - COMBUSTION ENGINES HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
Information Patent Grant
Printed wiring board mounted semiconductor device having leadframe...
- Patent number 5,521,427
- Issue date May 28, 1996
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High power dissipating packages with matched heatspreader heatsink...
- Patent number 5,463,529
- Issue date Oct 31, 1995
- LSI Logic Corporation
- Chok J. Chia
- F02 - COMBUSTION ENGINES HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
Information Patent Grant
Partially-molded, PCB chip carrier package for certain non-square d...
- Patent number 5,434,750
- Issue date Jul 18, 1995
- LSI Logic Corporation
- Michael D. Rostoker
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
High power dissipating packages with matched heatspreader heatsink...
- Patent number 5,353,193
- Issue date Oct 4, 1994
- LSI Logic Corporation
- Chok J. Chia
- F02 - COMBUSTION ENGINES HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
Information Patent Grant
Partially-molded, PCB chip carrier package
- Patent number 5,262,927
- Issue date Nov 16, 1993
- LSI Logic Corporation
- Chok J. Chia
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Modified lead frame for reducing wire wash in transfer molding of I...
- Patent number 5,197,183
- Issue date Mar 30, 1993
- LSI Logic Corporation
- Chok J. Chia
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor package with wire bond arrangement to reduce cross ta...
- Publication number 20060065983
- Publication date Mar 30, 2006
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Laser removal of plating tails for high speed packages
- Publication number 20060043565
- Publication date Mar 2, 2006
- Chok J. Chia
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Seng-Sooi Lim

Person

Patents Grantslast 30 patents

Integrated circuit package

Molded integrated circuit package

Overmold integrated circuit package

Mechanically interlocking ball grid array packages and method of ma...

Method for programming a substrate for array-type packages

Multiple layer tape ball grid array package

Grooved semiconductor die for flip-chip heat sink attachment

Molded array integrated circuit package

System and method for packaging an integrated circuit using encapsu...

Programmable substrate for array-type packages

Multiple sized die

Thermally enhanced tape ball grid array package

Process for using a removeable plating bus layer for high density s...

Apparatus and method for stackable molded lead frame ball grid arra...

Semiconductor device and fabrication method which advantageously co...

Overmolded package body on a substrate

Method of improving molding of an overmolded package body on a subs...

Process for manufacturing and mounting a semiconductor device leadf...

Partially-molded, PCB chip carrier package for certain non-square d...

Method of cooling a packaged electronic device

Printed wiring board mounted semiconductor device having leadframe...

High power dissipating packages with matched heatspreader heatsink...

Partially-molded, PCB chip carrier package for certain non-square d...

High power dissipating packages with matched heatspreader heatsink...

Partially-molded, PCB chip carrier package

Modified lead frame for reducing wire wash in transfer molding of I...

Patents Applicationslast 30 patents

Semiconductor package with wire bond arrangement to reduce cross ta...

Laser removal of plating tails for high speed packages