Seongmoon Wang

Person

Plainsboro, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for locating defective components of a circuit
- Patent number 8,214,172
- Issue date Jul 3, 2012
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Grant
Method for blocking unknown values in output response of scan test...
- Patent number 7,818,643
- Issue date Oct 19, 2010
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Grant
Test data compression method for system-on-chip using linear-feedba...
- Patent number 7,730,373
- Issue date Jun 1, 2010
- NEC Laboratories America, Inc.
- Zhanglei Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test output compaction with improved blocking of unknown values
- Patent number 7,610,527
- Issue date Oct 27, 2009
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Grant
Method for generating, from a test cube set, a generator configured...
- Patent number 7,610,540
- Issue date Oct 27, 2009
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing logic circuit designs
- Patent number 7,610,539
- Issue date Oct 27, 2009
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Grant
Re-configurable embedded core test protocol for system-on-chips (SO...
- Patent number 7,577,540
- Issue date Aug 18, 2009
- NEC Corporation
- Seongmoon Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for structured ASIC test point insertion
- Patent number 7,562,321
- Issue date Jul 14, 2009
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing logic circuit designs
- Patent number 7,484,151
- Issue date Jan 27, 2009
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Grant
Test output compaction for responses with unknown values
- Patent number 7,313,746
- Issue date Dec 25, 2007
- NEC Laboratories America, Inc.
- Chia-Tso Chao
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid scan-based delay testing technique for compact and high faul...
- Patent number 7,313,743
- Issue date Dec 25, 2007
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Test pattern compression with pattern-independent design-independen...
- Patent number 7,302,626
- Issue date Nov 27, 2007
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Grant
Externally-loaded weighted random test pattern compression
- Patent number 7,284,176
- Issue date Oct 16, 2007
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Grant
Test output compaction using response shaper
- Patent number 7,222,277
- Issue date May 22, 2007
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Grant
Restricted scan reordering technique to enhance delay fault coverage
- Patent number 7,188,323
- Issue date Mar 6, 2007
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Grant
Scalable scan-path test point insertion technique
- Patent number 7,131,081
- Issue date Oct 31, 2006
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Grant
Low hardware overhead scan based 3-weight weighted random BIST arch...
- Patent number 6,886,124
- Issue date Apr 26, 2005
- NEC Corporation
- Seongmoon Wang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR LOCATING DEFECTIVE COMPONENTS OF A CIRCUIT
- Publication number 20100121585
- Publication date May 13, 2010
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
MACHINE LEARNING BASED VOLUME DIAGNOSIS OF SEMICONDUCTOR CHIPS
- Publication number 20100005041
- Publication date Jan 7, 2010
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Blocking Unknown Values in Output Response of Scan Test...
- Publication number 20090210762
- Publication date Aug 20, 2009
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS
- Publication number 20090119563
- Publication date May 7, 2009
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS
- Publication number 20090119556
- Publication date May 7, 2009
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Application
Test Point Insertion and Scan Chain Reordering for Broadcast-Scan B...
- Publication number 20080195904
- Publication date Aug 14, 2008
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Partial Enhanced Scan Method for Reducing Volume of Delay Test Patt...
- Publication number 20080091998
- Publication date Apr 17, 2008
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Test Data Compression Method for System-On-Chip Using Linear-Feedba...
- Publication number 20080065940
- Publication date Mar 13, 2008
- NEC Laboratories America, Inc.
- Zhanglei Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Testing an Integrated Circuit
- Publication number 20070266283
- Publication date Nov 15, 2007
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Application
Method and Apparatus for Structured ASIC Test Point Insertion
- Publication number 20070136700
- Publication date Jun 14, 2007
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Testing Logic Circuit Designs
- Publication number 20070113129
- Publication date May 17, 2007
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Application
Test Output Compaction for Responses with Unknown Values
- Publication number 20070088999
- Publication date Apr 19, 2007
- NEC Laboratories America, Inc.
- Chia-Tso Chao
- G01 - MEASURING TESTING
Information Patent Application
Test Output Compaction with Improved Blocking of Unknown Values
- Publication number 20060236186
- Publication date Oct 19, 2006
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Test pattern compression with pattern-independent design-independen...
- Publication number 20060112320
- Publication date May 25, 2006
- NEC Laboratories America, Inc.
- Kedarnath Balakrishnan
- G01 - MEASURING TESTING
Information Patent Application
Test output compaction using response shaper
- Publication number 20060101316
- Publication date May 11, 2006
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Externally-loaded weighted random test pattern compression
- Publication number 20060015787
- Publication date Jan 19, 2006
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Restricted scan reordering technique to enhance delay fault coverage
- Publication number 20050235183
- Publication date Oct 20, 2005
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Hybrid scan-based delay testing technique for compact and high faul...
- Publication number 20050066242
- Publication date Mar 24, 2005
- NEC LABORATORIES AMERICA, INC
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Scalable scan-path test point insertion technique
- Publication number 20040177299
- Publication date Sep 9, 2004
- NEC Laboratories America, Inc.
- Seongmoon Wang
- G01 - MEASURING TESTING
Information Patent Application
Re-configurable embedded core test protocol for system-on-chips (SO...
- Publication number 20030167144
- Publication date Sep 4, 2003
- NEC USA, INC.
- Seongmoon Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low hardware overhead scan based 3-weight weighted random BIST arch...
- Publication number 20030149927
- Publication date Aug 7, 2003
- Seongmoon Wang
- G06 - COMPUTING CALCULATING COUNTING

Seongmoon Wang

Person

Patents Grantslast 30 patents

Systems and methods for locating defective components of a circuit

Method for blocking unknown values in output response of scan test...

Test data compression method for system-on-chip using linear-feedba...

Test output compaction with improved blocking of unknown values

Method for generating, from a test cube set, a generator configured...

Method and apparatus for testing logic circuit designs

Re-configurable embedded core test protocol for system-on-chips (SO...

Method and apparatus for structured ASIC test point insertion

Method and apparatus for testing logic circuit designs

Test output compaction for responses with unknown values

Hybrid scan-based delay testing technique for compact and high faul...

Test pattern compression with pattern-independent design-independen...

Externally-loaded weighted random test pattern compression

Test output compaction using response shaper

Restricted scan reordering technique to enhance delay fault coverage

Scalable scan-path test point insertion technique

Low hardware overhead scan based 3-weight weighted random BIST arch...

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR LOCATING DEFECTIVE COMPONENTS OF A CIRCUIT

MACHINE LEARNING BASED VOLUME DIAGNOSIS OF SEMICONDUCTOR CHIPS

Method for Blocking Unknown Values in Output Response of Scan Test...

METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS

METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS

Test Point Insertion and Scan Chain Reordering for Broadcast-Scan B...

Partial Enhanced Scan Method for Reducing Volume of Delay Test Patt...

Test Data Compression Method for System-On-Chip Using Linear-Feedba...

Method and Apparatus for Testing an Integrated Circuit

Method and Apparatus for Structured ASIC Test Point Insertion

Method and Apparatus for Testing Logic Circuit Designs

Test Output Compaction for Responses with Unknown Values

Test Output Compaction with Improved Blocking of Unknown Values

Test pattern compression with pattern-independent design-independen...

Test output compaction using response shaper

Externally-loaded weighted random test pattern compression

Restricted scan reordering technique to enhance delay fault coverage

Hybrid scan-based delay testing technique for compact and high faul...

Scalable scan-path test point insertion technique

Re-configurable embedded core test protocol for system-on-chips (SO...

Low hardware overhead scan based 3-weight weighted random BIST arch...