Sergey Gribok

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High performance regularized network-on-chip architecture
- Patent number 11,556,692
- Issue date Jan 17, 2023
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Geometric synthesis
- Patent number 11,467,804
- Issue date Oct 11, 2022
- Intel Corporation
- Sergey Vladimirovich Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing multiplier regularization
- Patent number 11,436,399
- Issue date Sep 6, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefix network-directed addition
- Patent number 11,334,318
- Issue date May 17, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning training architecture for programmable devices
- Patent number 11,210,063
- Issue date Dec 28, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing synthesis for field programmabl...
- Patent number 11,080,019
- Issue date Aug 3, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Continuous carry-chain packing
- Patent number 11,016,733
- Issue date May 25, 2021
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance regularized network-on-chip architecture
- Patent number 10,922,471
- Issue date Feb 16, 2021
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for using a multiplier to support multiple sub-multiplicati...
- Patent number 10,871,946
- Issue date Dec 22, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing an application aware system o...
- Patent number 10,867,090
- Issue date Dec 15, 2020
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuits with simultaneous dual function capability
- Patent number 10,790,829
- Issue date Sep 29, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for using a multiplier circuit to support multiple sub-mult...
- Patent number 10,732,932
- Issue date Aug 4, 2020
- Intel Corporation
- Bogdan Pasca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuits with augmented arithmetic densities
- Patent number 10,715,144
- Issue date Jul 14, 2020
- Intel Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improving system operation by replacing co...
- Patent number 10,223,488
- Issue date Mar 5, 2019
- Altera Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAM-based shift register with embedded addressing
- Patent number 10,102,892
- Issue date Oct 16, 2018
- Intel Corporation
- Sergey Gribok
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable node processing unit
- Patent number 9,239,704
- Issue date Jan 19, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Via-configurable high-performance logic block involving transistor...
- Patent number 8,957,398
- Issue date Feb 17, 2015
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for assigning code blocks to constituent decoder...
- Patent number 8,769,372
- Issue date Jul 1, 2014
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Via-configurable high-performance logic block architecture
- Patent number 8,735,857
- Issue date May 27, 2014
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock network fishbone architecture for a structured ASIC manufactu...
- Patent number 8,629,548
- Issue date Jan 14, 2014
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable node processing unit
- Patent number 8,443,033
- Issue date May 14, 2013
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
MEMS-based switching
- Patent number 8,436,700
- Issue date May 7, 2013
- eASIC Corporation
- Herman Schmit
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cryptographic random number generator using finite field operations
- Patent number 8,250,129
- Issue date Aug 21, 2012
- LSI Corporation
- Sergey Gribok
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for assigning code blocks to constituent decoder...
- Patent number 8,095,845
- Issue date Jan 10, 2012
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-byte cyclic redundancy check calculation circuit and method o...
- Patent number 8,095,848
- Issue date Jan 10, 2012
- LSI Corporation
- Sergey Y. Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for programmable decoding of a plurality of c...
- Patent number 8,035,537
- Issue date Oct 11, 2011
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel LDPC decoder
- Patent number 7,934,139
- Issue date Apr 26, 2011
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low complexity LDPC encoding algorithm
- Patent number 7,913,149
- Issue date Mar 22, 2011
- LSI Corporation
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for pipelined analog to digital conversion
- Patent number 7,656,340
- Issue date Feb 2, 2010
- LSI Corporation
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Built in self test transport controller architecture
- Patent number 7,546,505
- Issue date Jun 9, 2009
- LSI Corporation
- Sergey Gribok
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Modular Multipliers using Hybrid Reduction Techniques
- Publication number 20250013431
- Publication date Jan 9, 2025
- Altera Corporation
- Sergey Vladimirovich Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Iterative Multiplicative Reduction Circuit
- Publication number 20230273770
- Publication date Aug 31, 2023
- Intel Corporation
- Sergey Vladimirovich Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined Galois Counter Mode Hash Circuit
- Publication number 20230239136
- Publication date Jul 27, 2023
- Sergey Vladimirovich Gribok
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Power Savings by Register Insertion in Large Combinational Circuits
- Publication number 20230027064
- Publication date Jan 26, 2023
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Performance Systems And Methods For Modular Multiplication
- Publication number 20230026331
- Publication date Jan 26, 2023
- Intel Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retiming and Overclocking of Large Circuits
- Publication number 20230018414
- Publication date Jan 19, 2023
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES
- Publication number 20220107783
- Publication date Apr 7, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Performance Regularized Network-on-Chip Architecture
- Publication number 20210117607
- Publication date Apr 22, 2021
- Intel Corporation
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR USING A MULTIPLIER CIRCUIT TO SUPPORT MULTIPLE SUB-MULT...
- Publication number 20200142671
- Publication date May 7, 2020
- Intel Corporation
- Bogdan Pasca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC CIRCUITS WITH SIMULTANEOUS DUAL FUNCTION CAPABILITY
- Publication number 20200106442
- Publication date Apr 2, 2020
- Intel Corporation
- Martin LANGHAMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES
- Publication number 20200026494
- Publication date Jan 23, 2020
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Geometric Synthesis
- Publication number 20190324724
- Publication date Oct 24, 2019
- Sergey Vladimirovich Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Performance Regularized Network-on-Chip Architecture
- Publication number 20190318058
- Publication date Oct 17, 2019
- Gregg William Baeckler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC CIRCUITS WITH AUGMENTED ARITHMETIC DENSITIES
- Publication number 20190288688
- Publication date Sep 19, 2019
- Intel Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING AN APPLICATION AWARE SYSTEM O...
- Publication number 20190213289
- Publication date Jul 11, 2019
- Intel Corporation
- Gregg William BAECKLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING MULTIPLIER REGULARIZATION
- Publication number 20190121927
- Publication date Apr 25, 2019
- Intel Corporation
- Martin LANGHAMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Continuous Carry-Chain Packing
- Publication number 20190042200
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prefix Network-Directed Addition
- Publication number 20190042194
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING SYNTHESIS FOR FIELD PROGRAMMABL...
- Publication number 20190042683
- Publication date Feb 7, 2019
- Intel Corporation
- Martin LANGHAMMER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR USING A MULTIPLIER TO SUPPORT MULTIPLE SUB-MULTIPLICATI...
- Publication number 20190042198
- Publication date Feb 7, 2019
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Improving System Operation by Replacing Co...
- Publication number 20180025100
- Publication date Jan 25, 2018
- Altera Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digitally Controlled Delay Line for a Structured ASIC Having a Via...
- Publication number 20140103985
- Publication date Apr 17, 2014
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Via-Configurable High-Performance Logic Block Involving Transistor...
- Publication number 20140028348
- Publication date Jan 30, 2014
- eASIC Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variable Node Processing Unit
- Publication number 20130254252
- Publication date Sep 26, 2013
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cryptographic Random Number Generator Using Finite Field Operations
- Publication number 20120278372
- Publication date Nov 1, 2012
- LSI Corporation
- Sergey Gribok
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Via-Configurable High-Performance Logic Block Architecture
- Publication number 20120161093
- Publication date Jun 28, 2012
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER...
- Publication number 20120079345
- Publication date Mar 29, 2012
- LSI Corporation
- Alexander E. Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Parallel LDPC Decoder
- Publication number 20110173510
- Publication date Jul 14, 2011
- LSI Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Complexity LDPC Encoding Algorithm
- Publication number 20110099454
- Publication date Apr 28, 2011
- LSI Corporation
- Sergey Gribok
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMS-BASED SWITCHING
- Publication number 20110067982
- Publication date Mar 24, 2011
- eASIC Corporation
- Herman Schmit
- H01 - BASIC ELECTRIC ELEMENTS

Sergey Gribok

Person

Patents Grantslast 30 patents

High performance regularized network-on-chip architecture

Geometric synthesis

Method and apparatus for performing multiplier regularization

Prefix network-directed addition

Machine learning training architecture for programmable devices

Method and apparatus for performing synthesis for field programmabl...

Continuous carry-chain packing

High performance regularized network-on-chip architecture

Methods for using a multiplier to support multiple sub-multiplicati...

Method and apparatus for implementing an application aware system o...

Logic circuits with simultaneous dual function capability

Methods for using a multiplier circuit to support multiple sub-mult...

Logic circuits with augmented arithmetic densities

Method and apparatus for improving system operation by replacing co...

RAM-based shift register with embedded addressing

Variable node processing unit

Via-configurable high-performance logic block involving transistor...

System and method for assigning code blocks to constituent decoder...

Via-configurable high-performance logic block architecture

Clock network fishbone architecture for a structured ASIC manufactu...

Variable node processing unit

MEMS-based switching

Cryptographic random number generator using finite field operations

System and method for assigning code blocks to constituent decoder...

Multi-byte cyclic redundancy check calculation circuit and method o...

Methods and apparatus for programmable decoding of a plurality of c...

Parallel LDPC decoder

Low complexity LDPC encoding algorithm

Systems and methods for pipelined analog to digital conversion

Built in self test transport controller architecture

Patents Applicationslast 30 patents

Modular Multipliers using Hybrid Reduction Techniques

Iterative Multiplicative Reduction Circuit

Pipelined Galois Counter Mode Hash Circuit

Power Savings by Register Insertion in Large Combinational Circuits

High Performance Systems And Methods For Modular Multiplication

Retiming and Overclocking of Large Circuits

MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES

High Performance Regularized Network-on-Chip Architecture

METHODS FOR USING A MULTIPLIER CIRCUIT TO SUPPORT MULTIPLE SUB-MULT...

LOGIC CIRCUITS WITH SIMULTANEOUS DUAL FUNCTION CAPABILITY

MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES

Geometric Synthesis

High Performance Regularized Network-on-Chip Architecture

LOGIC CIRCUITS WITH AUGMENTED ARITHMETIC DENSITIES

METHOD AND APPARATUS FOR IMPLEMENTING AN APPLICATION AWARE SYSTEM O...

METHOD AND APPARATUS FOR PERFORMING MULTIPLIER REGULARIZATION

Continuous Carry-Chain Packing

Prefix Network-Directed Addition

METHOD AND APPARATUS FOR PERFORMING SYNTHESIS FOR FIELD PROGRAMMABL...

METHODS FOR USING A MULTIPLIER TO SUPPORT MULTIPLE SUB-MULTIPLICATI...

Method and Apparatus for Improving System Operation by Replacing Co...

Digitally Controlled Delay Line for a Structured ASIC Having a Via...

Via-Configurable High-Performance Logic Block Involving Transistor...

Variable Node Processing Unit

Cryptographic Random Number Generator Using Finite Field Operations

Via-Configurable High-Performance Logic Block Architecture

SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER...

Parallel LDPC Decoder

Low Complexity LDPC Encoding Algorithm

MEMS-BASED SWITCHING