Sey-Shing SUN

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low voltage embedded memory having conductive oxide and electrode s...
- Patent number 9,647,208
- Issue date May 9, 2017
- Intel Corporation
- Elijah V. Karpov
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage embedded memory having conductive oxide and electrode s...
- Patent number 9,231,204
- Issue date Jan 5, 2016
- Intel Corporation
- Elijah V. Karpov
- G11 - INFORMATION STORAGE
Information Patent Grant
Alternate pad structures/passivation inegration schemes to reduce o...
- Patent number 8,552,560
- Issue date Oct 8, 2013
- LSI Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Application of gate edge liner to maintain gate length CD in a repl...
- Patent number 8,384,165
- Issue date Feb 26, 2013
- LSI Corporation
- Richard J. Carter
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Reduction of macro level stresses in copper/low-K wafers
- Patent number 8,076,779
- Issue date Dec 13, 2011
- LSI Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bi-axial texturing of high-K dielectric films to reduce leakage cur...
- Patent number 7,956,401
- Issue date Jun 7, 2011
- LSI Corporation
- Wai Lo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Self-aligned cell integration scheme
- Patent number 7,915,122
- Issue date Mar 29, 2011
- Nantero, Inc.
- Richard J. Carter
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Bi-axial texturing of high-K dielectric films to reduce leakage cur...
- Patent number 7,619,272
- Issue date Nov 17, 2009
- LSI Corporation
- Wai Lo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for redirecting void diffusion away from vias in an integrat...
- Patent number 7,582,566
- Issue date Sep 1, 2009
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Patent number 7,531,442
- Issue date May 12, 2009
- LSI Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for diverting void diffusion in integrated cir...
- Patent number 7,436,040
- Issue date Oct 14, 2008
- LSI Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Application of gate edge liner to maintain gate length CD in a repl...
- Patent number 7,405,116
- Issue date Jul 29, 2008
- LSI Corporation
- Richard J. Carter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nano structure electrode design
- Patent number 7,402,770
- Issue date Jul 22, 2008
- LSI Logic Corporation
- Sey-Shing Sun
- G11 - INFORMATION STORAGE
Information Patent Grant
Damascene replacement metal gate process with controlled gate profi...
- Patent number 7,365,015
- Issue date Apr 29, 2008
- LSI Logic Corporation
- Hong Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for redirecting void diffusion away from vias...
- Patent number 7,361,965
- Issue date Apr 22, 2008
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Incorporating dopants to enhance the dielectric properties of metal...
- Patent number 7,312,127
- Issue date Dec 25, 2007
- LSI Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated barrier and seed layer for copper interconnect technology
- Patent number 7,300,869
- Issue date Nov 27, 2007
- LSI Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduce or eliminate IMC cracking in post wire bonded dies by doping...
- Patent number 7,205,673
- Issue date Apr 17, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for creating ultra low resistance damascene co...
- Patent number 7,196,420
- Issue date Mar 27, 2007
- LSI Logic Corporation
- Peter A. Burke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating planar semiconductor wafers
- Patent number 7,179,736
- Issue date Feb 20, 2007
- LSI Logic Corporation
- Byung-Sung Leo Kwak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Incorporating dopants to enhance the dielectric properties of metal...
- Patent number 7,064,062
- Issue date Jun 20, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bimetallic oxide compositions for gate dielectrics
- Patent number 7,015,096
- Issue date Mar 21, 2006
- LSI Logic Corporation
- Vladimir Zubkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating barrier layers for copper diffusion
- Patent number 6,998,343
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Grace Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for creating ultra low resistance damascene co...
- Patent number 6,987,059
- Issue date Jan 17, 2006
- LSI Logic Corporation
- Peter A. Burke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carbon nanotube memory cell for integrated circuit structure with r...
- Patent number 6,955,937
- Issue date Oct 18, 2005
- LSI Logic Corporation
- Peter A. Burke
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LOW VOLTAGE EMBEDDED MEMORY HAVING CONDUCTIVE OXIDE AND ELECTRODE S...
- Publication number 20160079523
- Publication date Mar 17, 2016
- Elijah V. Karpov
- G11 - INFORMATION STORAGE
Information Patent Application
LOW VOLTAGE EMBEDDED MEMORY HAVING CONDUCTIVE OXIDE AND ELECTRODE S...
- Publication number 20140092666
- Publication date Apr 3, 2014
- Elijah V. Karpov
- G11 - INFORMATION STORAGE
Information Patent Application
ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE...
- Publication number 20140030541
- Publication date Jan 30, 2014
- LSI Corporation
- Hemanshu Bhatt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CUR...
- Publication number 20100022060
- Publication date Jan 28, 2010
- LSI Corporation
- Wai LO
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPL...
- Publication number 20080308882
- Publication date Dec 18, 2008
- LSI Corporation
- Richard J. Carter
- G02 - OPTICS
Information Patent Application
DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFI...
- Publication number 20080150090
- Publication date Jun 26, 2008
- LSI Logic Corporation
- Hong Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRAT...
- Publication number 20080132065
- Publication date Jun 5, 2008
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for diverting void diffusion in integrated cir...
- Publication number 20070259518
- Publication date Nov 8, 2007
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for redirecting void diffusion away from vias...
- Publication number 20070155160
- Publication date Jul 5, 2007
- LSI Logic Corporation
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Publication number 20070123024
- Publication date May 31, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Alternate pad structures/passivation inegration schemes to reduce o...
- Publication number 20070114667
- Publication date May 24, 2007
- LSI Logic Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Reduction of macro level stresses in copper/Low-K wafers by alterin...
- Publication number 20070102812
- Publication date May 10, 2007
- LSI Logic Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nano structure electrode design
- Publication number 20060278902
- Publication date Dec 14, 2006
- Sey-Shing Sun
- G11 - INFORMATION STORAGE
Information Patent Application
Self-aligned cell integration scheme
- Publication number 20060281256
- Publication date Dec 14, 2006
- Richard J. Carter
- B82 - NANO-TECHNOLOGY
Information Patent Application
Incorporating dopants to enhance the dielectric properties of metal...
- Publication number 20060166496
- Publication date Jul 27, 2006
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bi-axial texturing of high-K dielectric films to reduce leakage cur...
- Publication number 20060118919
- Publication date Jun 8, 2006
- LSI Logic Corporation, a Delaware Corporation
- Wai Lo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Method for fabricating planar semiconductor wafers
- Publication number 20060084267
- Publication date Apr 20, 2006
- LSI Logic Corporation, A Delaware Corporation
- Byung-Sung Leo Kwak
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Integrated barrier and seed layer for copper interconnect technology
- Publication number 20060063375
- Publication date Mar 23, 2006
- LSI Logic Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Application of gate edge liner to maintain gate length CD in a repl...
- Publication number 20060035425
- Publication date Feb 16, 2006
- Richard J. Carter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Damascene replacement metal gate process with controlled gate profi...
- Publication number 20060011994
- Publication date Jan 19, 2006
- Hong Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improved local planarity control during electropolishing
- Publication number 20050224358
- Publication date Oct 13, 2005
- LSI Logic Corporation
- Byung-Sung Kwak
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Incorporating dopants to enhance the dielectric properties of metal...
- Publication number 20050127458
- Publication date Jun 16, 2005
- LSI Logic Corporation
- Wai Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating an alloy cap layer over CU wires to improve e...
- Publication number 20040207093
- Publication date Oct 21, 2004
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS

Sey-Shing SUN

Person

Patents Grantslast 30 patents

Low voltage embedded memory having conductive oxide and electrode s...

Low voltage embedded memory having conductive oxide and electrode s...

Alternate pad structures/passivation inegration schemes to reduce o...

Application of gate edge liner to maintain gate length CD in a repl...

Reduction of macro level stresses in copper/low-K wafers

Bi-axial texturing of high-K dielectric films to reduce leakage cur...

Self-aligned cell integration scheme

Bi-axial texturing of high-K dielectric films to reduce leakage cur...

Method for redirecting void diffusion away from vias in an integrat...

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Method and apparatus for diverting void diffusion in integrated cir...

Application of gate edge liner to maintain gate length CD in a repl...

Nano structure electrode design

Damascene replacement metal gate process with controlled gate profi...

Method and apparatus for redirecting void diffusion away from vias...

Incorporating dopants to enhance the dielectric properties of metal...

Integrated barrier and seed layer for copper interconnect technology

Reduce or eliminate IMC cracking in post wire bonded dies by doping...

Method and structure for creating ultra low resistance damascene co...

Method for fabricating planar semiconductor wafers

Incorporating dopants to enhance the dielectric properties of metal...

Bimetallic oxide compositions for gate dielectrics

Method for creating barrier layers for copper diffusion

Method and structure for creating ultra low resistance damascene co...

Carbon nanotube memory cell for integrated circuit structure with r...

Patents Applicationslast 30 patents

LOW VOLTAGE EMBEDDED MEMORY HAVING CONDUCTIVE OXIDE AND ELECTRODE S...

LOW VOLTAGE EMBEDDED MEMORY HAVING CONDUCTIVE OXIDE AND ELECTRODE S...

ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE...

BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CUR...

APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPL...

DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFI...

METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRAT...

Method and apparatus for diverting void diffusion in integrated cir...

Method and apparatus for redirecting void diffusion away from vias...

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Alternate pad structures/passivation inegration schemes to reduce o...

Reduction of macro level stresses in copper/Low-K wafers by alterin...

Nano structure electrode design

Self-aligned cell integration scheme

Incorporating dopants to enhance the dielectric properties of metal...

Bi-axial texturing of high-K dielectric films to reduce leakage cur...

Method for fabricating planar semiconductor wafers

Integrated barrier and seed layer for copper interconnect technology

Application of gate edge liner to maintain gate length CD in a repl...

Damascene replacement metal gate process with controlled gate profi...

Method for improved local planarity control during electropolishing

Incorporating dopants to enhance the dielectric properties of metal...

Method of fabricating an alloy cap layer over CU wires to improve e...