Shahram Jamshidi

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Cupertino, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Domino circuit with disable feature
- Patent number 7,592,840
- Issue date Sep 22, 2009
- Intel Corporation
- Kin Yip Sit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gate-clocked domino circuits with reduced leakage current
- Patent number 6,952,118
- Issue date Oct 4, 2005
- Intel Corporation
- Shahram Jamshidi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power entry latch to interface static logic with dynamic logic
- Patent number 6,707,318
- Issue date Mar 16, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Plurality of distinct multiplexers that operate as a single multipl...
- Patent number 5,646,558
- Issue date Jul 8, 1997
- Intel Corporation
- Shahram Jamshidi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplexer having a plurality of internal data paths that operate...
- Patent number 5,625,303
- Issue date Apr 29, 1997
- Intel Corporation
- Shahram Jamshidi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed reduced area multiplexer
- Patent number 5,598,114
- Issue date Jan 28, 1997
- Intel Corporation
- Shahram Jamshidi
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DOMINO CIRCUIT WITH DISABLE FEATURE
- Publication number 20080106302
- Publication date May 8, 2008
- Kin Yip Sit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Gate-clocked domino circuits with reduced leakage current
- Publication number 20040119503
- Publication date Jun 24, 2004
- Shahram Jamshidi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low power entry latch to interface static logic with dynamic logic
- Publication number 20030184344
- Publication date Oct 2, 2003
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY