Shankar SINHA

Person

Redwood Shores, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dielectric extension to mitigate short channel effects
- Patent number 9,318,333
- Issue date Apr 19, 2016
- Cypress Semiconductor Corporation
- Vidyut Gopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier region underlying source/drain regions for dual-bit memory...
- Patent number 9,171,936
- Issue date Oct 27, 2015
- Cypress Semiconductor Corporation
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an electronic device including forming a charge s...
- Patent number 8,409,952
- Issue date Apr 2, 2013
- Spansion LLC
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device with buried bit line structure
- Patent number 8,148,770
- Issue date Apr 3, 2012
- Spansion LLC
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using thick spacer for bitline implant then remove
- Patent number 7,888,218
- Issue date Feb 15, 2011
- Spansion LLC
- Zhizheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell dual pocket implant
- Patent number 7,678,674
- Issue date Mar 16, 2010
- Spansion LLC
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Select transistor using buried bit line from core
- Patent number 7,561,457
- Issue date Jul 14, 2009
- Spansion LLC
- Mark Randolph
- G11 - INFORMATION STORAGE
Information Patent Grant
Aggressive cleaning process for semiconductor device contact formation
- Patent number 7,476,604
- Issue date Jan 13, 2009
- Advanced Micro Devices, Inc.
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming a memory device
- Patent number 7,269,067
- Issue date Sep 11, 2007
- Spansion LLC
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Silicide MOSFET architecture and method of manufacture
- Patent number 6,642,119
- Issue date Nov 4, 2003
- Advanced Micro Devices, Inc.
- Mario M. Pelella
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE S...
- Publication number 20090256242
- Publication date Oct 15, 2009
- SPANSION LLC
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dielectric extension to mitigate short channel effects
- Publication number 20080157199
- Publication date Jul 3, 2008
- Spansion LLC
- Vidyut Gopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Using thick spacer for bitline implant then remove
- Publication number 20080153223
- Publication date Jun 26, 2008
- Spansion LLC
- Zhizheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Barrier region for memory devices
- Publication number 20080135902
- Publication date Jun 12, 2008
- Spansion LLC
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE
- Publication number 20080123384
- Publication date May 29, 2008
- SPANSION LLC
- Mark RANDOLPH
- G11 - INFORMATION STORAGE
Information Patent Application
Method for programming a memory device
- Publication number 20070008782
- Publication date Jan 11, 2007
- Shankar Sinha
- G11 - INFORMATION STORAGE

Shankar SINHA

Person

Patents Grantslast 30 patents

Dielectric extension to mitigate short channel effects

Barrier region underlying source/drain regions for dual-bit memory...

Method of forming an electronic device including forming a charge s...

Memory device with buried bit line structure

Using thick spacer for bitline implant then remove

Memory cell dual pocket implant

Select transistor using buried bit line from core

Aggressive cleaning process for semiconductor device contact formation

Programming a memory device

Silicide MOSFET architecture and method of manufacture

Patents Applicationslast 30 patents

METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE S...

Dielectric extension to mitigate short channel effects

Using thick spacer for bitline implant then remove

Barrier region for memory devices

SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE

Method for programming a memory device