Sharad Gupta

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Power supply circuit with reduced leakage current
- Patent number 12,047,073
- Issue date Jul 23, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory circuit architecture with multiplexing between memory banks
- Patent number 12,020,766
- Issue date Jun 25, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power and robust level-shifting pulse latch for dual-power memo...
- Patent number 11,972,834
- Issue date Apr 30, 2024
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed multi-port memory supporting collision
- Patent number 11,955,169
- Issue date Apr 9, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with scan chain testing of column redundancy logic and multi...
- Patent number 11,935,606
- Issue date Mar 19, 2024
- QUALCOMM Incorporated
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with efficient DVS controlled by asynchronous inputs
- Patent number 11,837,313
- Issue date Dec 5, 2023
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Wide voltage range level shifter with reduced duty cycle distortion...
- Patent number 11,228,312
- Issue date Jan 18, 2022
- QUALCOMM Incorporated
- Narender Ponna
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for control signal latching in memories
- Patent number 11,152,921
- Issue date Oct 19, 2021
- QUALCOMM Incorporated
- Veerabhadra Rao Boda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write assist circuitry for memory
- Patent number 11,049,552
- Issue date Jun 29, 2021
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Reusing a cell block for hybrid dual write
- Patent number 11,043,271
- Issue date Jun 22, 2021
- Western Digital Technologies, Inc.
- Arun Kumar Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell block allocation for hybrid dual write
- Patent number 11,037,627
- Issue date Jun 15, 2021
- Western Digital Technologies, Inc.
- Arun Kumar Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area efficient write data path circuit for SRAM yield enhancement
- Patent number 10,867,668
- Issue date Dec 15, 2020
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM write yield enhancement with pull-up strength modulation
- Patent number 10,811,086
- Issue date Oct 20, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE
Information Patent Grant
Access assist with wordline adjustment with tracking cell
- Patent number 10,811,088
- Issue date Oct 20, 2020
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Logical grouping for hybrid dual write
- Patent number 10,732,838
- Issue date Aug 4, 2020
- Western Digital Technologies, Inc.
- Noor Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics server and method for streaming rendered content via a rem...
- Patent number 10,560,698
- Issue date Feb 11, 2020
- NVIDIA Corporation
- Thomas Meier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible power sequencing for dual-power memory
- Patent number 10,446,196
- Issue date Oct 15, 2019
- QUALCOMM Incorporated
- Mukund Narasimhan
- G11 - INFORMATION STORAGE
Information Patent Grant
Graphics server and method for streaming rendered content via a rem...
- Patent number 10,154,265
- Issue date Dec 11, 2018
- NVIDIA Corporation
- Thomas Meier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Noise immune data path scheme for multi-bank memory architecture
- Patent number 10,140,224
- Issue date Nov 27, 2018
- QUALCOMM Incorporated
- Mukund Narasimhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing design for testability (DFT)...
- Patent number 9,947,419
- Issue date Apr 17, 2018
- QUALCOMM Incorporated
- Rakesh Kumar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline adjustment scheme
- Patent number 9,928,898
- Issue date Mar 27, 2018
- QUALCOMM Incorporated
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline precharge control and tracking scheme providing increased m...
- Patent number 9,928,889
- Issue date Mar 27, 2018
- Qualcomm Incorporation
- Mukund Narasimhan
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit writability implementation for memories
- Patent number 9,875,776
- Issue date Jan 23, 2018
- QUALCOMM Incorporated
- Priyankar Mathuria
- G11 - INFORMATION STORAGE
Information Patent Grant
Boost charge recycle for low-power memory
- Patent number 9,875,790
- Issue date Jan 23, 2018
- QUALCOMM Incorporated
- Rakesh Kumar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a word line assertion delayed by a bit line discharge f...
- Patent number 9,865,316
- Issue date Jan 9, 2018
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for controlling boost capacitance for low powe...
- Patent number 9,837,144
- Issue date Dec 5, 2017
- QUALCOMM Incorporated
- Rakesh Kumar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture to improve write-ability in SRAM
- Patent number 9,721,650
- Issue date Aug 1, 2017
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse latch reset tracking at high differential voltage
- Patent number 9,607,674
- Issue date Mar 28, 2017
- QUALCOMM Incorporated
- Mukund Narasimhan
- G11 - INFORMATION STORAGE
Information Patent Grant
Error prediction in logic and memory devices
- Patent number 9,218,892
- Issue date Dec 22, 2015
- Texas Instruments Incorporated
- Dharin N Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Error prediction in logic and memory devices
- Patent number 8,762,804
- Issue date Jun 24, 2014
- Texas Instruments Incorporated
- Dharin N Shah
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20240312496
- Publication date Sep 19, 2024
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with Scan Chain Testing of Column Redundancy Logic and Multi...
- Publication number 20240221853
- Publication date Jul 4, 2024
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
- Publication number 20240221828
- Publication date Jul 4, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS
- Publication number 20230290387
- Publication date Sep 14, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT
- Publication number 20230179183
- Publication date Jun 8, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS
- Publication number 20230139283
- Publication date May 4, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTI...
- Publication number 20230005556
- Publication date Jan 5, 2023
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION
- Publication number 20220310156
- Publication date Sep 29, 2022
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
Low Power and Robust Level-Shifting Pulse Latch for Dual-Power Memo...
- Publication number 20220293148
- Publication date Sep 15, 2022
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Application
WIDE VOLTAGE RANGE LEVEL SHIFTER WITH REDUCED DUTY CYCLE DISTORTION...
- Publication number 20220021389
- Publication date Jan 20, 2022
- QUALCOMM Incorporated
- Narender PONNA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL
- Publication number 20200294580
- Publication date Sep 17, 2020
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Application
CELL BLOCK ALLOCATION FOR HYBRID DUAL WRITE
- Publication number 20190163386
- Publication date May 30, 2019
- Western Digital Technologies, Inc.
- Arun Kumar Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REUSING A CELL BLOCK FOR HYBRID DUAL WRITE
- Publication number 20190164598
- Publication date May 30, 2019
- Western Digital Technologies, Inc.
- Arun Kumar Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGICAL GROUPING FOR HYBRID DUAL WRITE
- Publication number 20190163369
- Publication date May 30, 2019
- Western Digital Technologies, Inc.
- Noor Mohamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT
- Publication number 20190108872
- Publication date Apr 11, 2019
- QUALCOMM Incorporated
- Sharad Kumar GUPTA
- G11 - INFORMATION STORAGE
Information Patent Application
GRAPHICS SERVER AND METHOD FOR STREAMING RENDERED CONTENT VIA A REM...
- Publication number 20190075297
- Publication date Mar 7, 2019
- NVIDIA Corporation
- Thomas Meier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE
- Publication number 20180113821
- Publication date Apr 26, 2018
- QUALCOMM Incorporated
- Mukund NARASIMHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORDLINE ADJUSTMENT SCHEME
- Publication number 20170287551
- Publication date Oct 5, 2017
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH IMPROVED WRITE TIME AND REDUCED WRITE POWER
- Publication number 20170213587
- Publication date Jul 27, 2017
- QUALCOMM Incorporated
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR PREDICTION IN LOGIC AND MEMORY DEVICES
- Publication number 20150082105
- Publication date Mar 19, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Dharin N. Shah
- G11 - INFORMATION STORAGE
Information Patent Application
GRAPHICS SERVER AND METHOD FOR STREAMING RENDERED CONTENT VIA A REM...
- Publication number 20140376606
- Publication date Dec 25, 2014
- Thomas Meier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ERROR PREDICTION IN LOGIC AND MEMORY DEVICES
- Publication number 20140040692
- Publication date Feb 6, 2014
- Texas Instruments, Incorporated
- Dharin N. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CIRCUIT AND A TRACKING CIRCUIT THEREOF
- Publication number 20120163109
- Publication date Jun 28, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Santhosh Narayanaswamy
- G11 - INFORMATION STORAGE
Information Patent Application
EDGE-SENSITIVE FEEDBACK-CONTROLLED PULSE GENERATOR
- Publication number 20110018602
- Publication date Jan 27, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Shahid ALI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEGMENTED TERNARY CONTENT ADDRESSABLE MEMORY SEARCH ARCHITECTURE
- Publication number 20100165690
- Publication date Jul 1, 2010
- Sharad Kumar Gupta
- G11 - INFORMATION STORAGE
Information Patent Application
CONTENT ADDRESSABLE MEMORY BASED ON A RIPPLE SEARCH SCHEME
- Publication number 20090290399
- Publication date Nov 26, 2009
- SHAHID ALI
- G11 - INFORMATION STORAGE
Information Patent Application
BIT CELL DESIGNS FOR TERNARY CONTENT ADDRESSABLE MEMORY
- Publication number 20090290400
- Publication date Nov 26, 2009
- SHAHID ALI
- G11 - INFORMATION STORAGE

Sharad Gupta

Person

Patents Grantslast 30 patents

Power supply circuit with reduced leakage current

Memory circuit architecture with multiplexing between memory banks

Low power and robust level-shifting pulse latch for dual-power memo...

High-speed multi-port memory supporting collision

Memory with scan chain testing of column redundancy logic and multi...

Memory with efficient DVS controlled by asynchronous inputs

Wide voltage range level shifter with reduced duty cycle distortion...

Systems and methods for control signal latching in memories

Write assist circuitry for memory

Reusing a cell block for hybrid dual write

Cell block allocation for hybrid dual write

Area efficient write data path circuit for SRAM yield enhancement

SRAM write yield enhancement with pull-up strength modulation

Access assist with wordline adjustment with tracking cell

Logical grouping for hybrid dual write

Graphics server and method for streaming rendered content via a rem...

Flexible power sequencing for dual-power memory

Graphics server and method for streaming rendered content via a rem...

Noise immune data path scheme for multi-bank memory architecture

Apparatus and method for implementing design for testability (DFT)...

Wordline adjustment scheme

Bitline precharge control and tracking scheme providing increased m...

Bit writability implementation for memories

Boost charge recycle for low-power memory

Memory with a word line assertion delayed by a bit line discharge f...

Apparatus and method for controlling boost capacitance for low powe...

Architecture to improve write-ability in SRAM

Pulse latch reset tracking at high differential voltage

Error prediction in logic and memory devices

Error prediction in logic and memory devices

Patents Applicationslast 30 patents

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

Memory with Scan Chain Testing of Column Redundancy Logic and Multi...

HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION

MEMORY CIRCUIT ARCHITECTURE WITH MULTIPLEXING BETWEEN MEMORY BANKS

POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT

MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS

MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTI...

HIGH-SPEED MULTI-PORT MEMORY SUPPORTING COLLISION

Low Power and Robust Level-Shifting Pulse Latch for Dual-Power Memo...

WIDE VOLTAGE RANGE LEVEL SHIFTER WITH REDUCED DUTY CYCLE DISTORTION...

ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL

CELL BLOCK ALLOCATION FOR HYBRID DUAL WRITE

REUSING A CELL BLOCK FOR HYBRID DUAL WRITE

LOGICAL GROUPING FOR HYBRID DUAL WRITE

AREA EFFICIENT WRITE DATA PATH CIRCUIT FOR SRAM YIELD ENHANCEMENT

GRAPHICS SERVER AND METHOD FOR STREAMING RENDERED CONTENT VIA A REM...

NOISE IMMUNE DATA PATH SCHEME FOR MULTI-BANK MEMORY ARCHITECTURE

WORDLINE ADJUSTMENT SCHEME

MEMORY WITH IMPROVED WRITE TIME AND REDUCED WRITE POWER

ERROR PREDICTION IN LOGIC AND MEMORY DEVICES

GRAPHICS SERVER AND METHOD FOR STREAMING RENDERED CONTENT VIA A REM...

ERROR PREDICTION IN LOGIC AND MEMORY DEVICES

MEMORY CIRCUIT AND A TRACKING CIRCUIT THEREOF

EDGE-SENSITIVE FEEDBACK-CONTROLLED PULSE GENERATOR

SEGMENTED TERNARY CONTENT ADDRESSABLE MEMORY SEARCH ARCHITECTURE

CONTENT ADDRESSABLE MEMORY BASED ON A RIPPLE SEARCH SCHEME

BIT CELL DESIGNS FOR TERNARY CONTENT ADDRESSABLE MEMORY