Sharad Malik

Person

Princeton, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for efficient implementation of boolean satisfiab...
- Patent number 7,418,369
- Issue date Aug 26, 2008
- The Trustees of Princeton University
- Matthew Moskewicz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,961,916
- Issue date Nov 1, 2005
- Synopsys, Inc.
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design validation using retiming
- Patent number 6,874,135
- Issue date Mar 29, 2005
- NEC Corporation
- Aarti Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partition-based decision heuristics for SAT and image computation u...
- Patent number 6,651,234
- Issue date Nov 18, 2003
- NEC Corporation
- Aarti Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for accurate and efficient updates of timing information log...
- Patent number 6,449,756
- Issue date Sep 10, 2002
- Monterey Design Systems
- Sharad Malik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,442,743
- Issue date Aug 27, 2002
- Monterey Design Systems
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrent buffer insertion and placement of...
- Patent number 6,367,051
- Issue date Apr 2, 2002
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design optimization using logical and physical information
- Patent number 6,286,128
- Issue date Sep 4, 2001
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable hardware system implementing Boolean Satisfiability an...
- Patent number 6,247,164
- Issue date Jun 12, 2001
- NEC USA, Inc.
- Pranav Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for logic optimization for improving timing and congestion d...
- Patent number 6,192,508
- Issue date Feb 20, 2001
- Monterey Design Systems
- Sharad Malik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementation of boolean satisfiability with non-chronological bac...
- Patent number 6,038,392
- Issue date Mar 14, 2000
- NEC USA, Inc.
- Pranav Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for using complete-1-distinguishability for FSM equivalence...
- Patent number 6,035,109
- Issue date Mar 7, 2000
- NEC USA, Inc.
- Pranav N Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced binary decision diagram-based functional simulation
- Patent number 5,937,183
- Issue date Aug 10, 1999
- NEC USA, Inc.
- Pranav N. Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for processing graphic delay data of logic circui...
- Patent number 5,841,673
- Issue date Nov 24, 1998
- NEC Corporation
- Noriya Kobayashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of finding minimum-cost feedback-vertex sets for a graph for...
- Patent number 5,522,063
- Issue date May 28, 1996
- NEC USA, Inc.
- Pranav N. Ashar
- G01 - MEASURING TESTING
Information Patent Grant
Timing analysis of VLSI circuits
- Patent number 5,457,638
- Issue date Oct 10, 1995
- NEC Research Institue, Inc.
- Pranav Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exploiting multi-cycle false paths in the performance optimization...
- Patent number 5,448,497
- Issue date Sep 5, 1995
- NEC Research Institute, Inc.
- Pranav Ashar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method for design validation using retiming
- Publication number 20050149301
- Publication date Jul 7, 2005
- NEC Corporation
- Aarti Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DESIGN VALIDATION USING RETIMING
- Publication number 20030182638
- Publication date Sep 25, 2003
- AARTI GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for efficient implementation of boolean satisfiab...
- Publication number 20030084411
- Publication date May 1, 2003
- Matthew Moskewicz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partition-based decision heuristics for SAT and image computation u...
- Publication number 20020178424
- Publication date Nov 28, 2002
- NEC USA, INC.
- Aarti Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement method for integrated circuit design using topo-clustering
- Publication number 20020138816
- Publication date Sep 26, 2002
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING

Sharad Malik

Person

Patents Grantslast 30 patents

Method and system for efficient implementation of boolean satisfiab...

Placement method for integrated circuit design using topo-clustering

Method for design validation using retiming

Partition-based decision heuristics for SAT and image computation u...

Method for accurate and efficient updates of timing information log...

Placement method for integrated circuit design using topo-clustering

System and method for concurrent buffer insertion and placement of...

Method for design optimization using logical and physical information

Configurable hardware system implementing Boolean Satisfiability an...

Method for logic optimization for improving timing and congestion d...

Implementation of boolean satisfiability with non-chronological bac...

Method for using complete-1-distinguishability for FSM equivalence...

Enhanced binary decision diagram-based functional simulation

System and method for processing graphic delay data of logic circui...

Method of finding minimum-cost feedback-vertex sets for a graph for...

Timing analysis of VLSI circuits

Exploiting multi-cycle false paths in the performance optimization...

Patents Applicationslast 30 patents

Method for design validation using retiming

METHOD FOR DESIGN VALIDATION USING RETIMING

Method and system for efficient implementation of boolean satisfiab...

Partition-based decision heuristics for SAT and image computation u...

Placement method for integrated circuit design using topo-clustering