Shay Reboh

Person

Guilderland, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of making a transistor having a source and a drain obtained...
- Patent number 10,170,621
- Issue date Jan 1, 2019
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Shay Reboh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of producing a channel structure formed from a plurality of...
- Patent number 10,141,424
- Issue date Nov 27, 2018
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Remi Coquand
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a transistor having a vertical channel havin...
- Patent number 10,134,875
- Issue date Nov 20, 2018
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Shay Reboh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recrystallization of source and drain blocks from above
- Patent number 9,246,006
- Issue date Jan 26, 2016
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Perrine Batude
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
GATE CONTACT AT GATE ENDS THROUGH BACKSIDE GATE CUT
- Publication number 20250089288
- Publication date Mar 13, 2025
- International Business Machines Corporation
- Tao Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HANDLER WAFER WITH LOW OVERLAY RESIDUAL BACKSIDE PATTERNING
- Publication number 20250087527
- Publication date Mar 13, 2025
- International Business Machines Corporation
- Prabudhya Roy Chowdhury
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FET WITH BOTTOM EPI SIZE CONTROL AND WRAPAROUND BACKSIDE CO...
- Publication number 20250062190
- Publication date Feb 20, 2025
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE BACKSIDE ISOLATION FEATURE INTEGRATION
- Publication number 20250056865
- Publication date Feb 13, 2025
- International Business Machines Corporation
- Tao Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FIELD EFFECT TRANSISTORS
- Publication number 20250048688
- Publication date Feb 6, 2025
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FIELD EFFECT TRANSISTOR HYBRID GATE CUT
- Publication number 20250040240
- Publication date Jan 30, 2025
- International Business Machines Corporation
- Shay Reboh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRANSISTORS WITH DIELECTRIC INSULATOR LAYERS
- Publication number 20250006730
- Publication date Jan 2, 2025
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A TRANSISTOR HAVING A VERTICAL CHANNEL HAVIN...
- Publication number 20180204931
- Publication date Jul 19, 2018
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Shay REBOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PRODUCING A CHANNEL STRUCTURE FORMED FROM A PLURALITY OF...
- Publication number 20170345915
- Publication date Nov 30, 2017
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Remi COQUAND
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A TRANSISTOR HAVING A SOURCE AND A DRAIN OBTAINED...
- Publication number 20170345931
- Publication date Nov 30, 2017
- Shay REBOH
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Method of making a transistor having a source and a drain obtained...

Method of producing a channel structure formed from a plurality of...

Method for fabricating a transistor having a vertical channel havin...

Recrystallization of source and drain blocks from above

Patents Applicationslast 30 patents

GATE CONTACT AT GATE ENDS THROUGH BACKSIDE GATE CUT

HANDLER WAFER WITH LOW OVERLAY RESIDUAL BACKSIDE PATTERNING

STACKED FET WITH BOTTOM EPI SIZE CONTROL AND WRAPAROUND BACKSIDE CO...

SEMICONDUCTOR DEVICE BACKSIDE ISOLATION FEATURE INTEGRATION

STACKED FIELD EFFECT TRANSISTORS

STACKED FIELD EFFECT TRANSISTOR HYBRID GATE CUT

STACKED TRANSISTORS WITH DIELECTRIC INSULATOR LAYERS

METHOD FOR FABRICATING A TRANSISTOR HAVING A VERTICAL CHANNEL HAVIN...

METHOD OF PRODUCING A CHANNEL STRUCTURE FORMED FROM A PLURALITY OF...

METHOD OF MAKING A TRANSISTOR HAVING A SOURCE AND A DRAIN OBTAINED...