Shreesh Narasimha

Person

Yorktown Heights, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 11,101,357
- Issue date Aug 24, 2021
- Tessera, Inc.
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming interconnect without gate cut isolation blocking opening fo...
- Patent number 11,056,398
- Issue date Jul 6, 2021
- GLOBALFOUNDRIES U.S. INC.
- Daniel J. Jaeger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with self-aligned and non-self-aligned con...
- Patent number 10,833,160
- Issue date Nov 10, 2020
- GLOBALFOUNDRIES Inc.
- Michael Aquilino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 10,734,492
- Issue date Aug 4, 2020
- Tessera, Inc.
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with integrated passive structures
- Patent number 10,580,686
- Issue date Mar 3, 2020
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 10,381,452
- Issue date Aug 13, 2019
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 10,374,048
- Issue date Aug 6, 2019
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 10,367,072
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with integrated passive structures
- Patent number 10,242,906
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin fabrication process with dual shallow trench isolation and tuna...
- Patent number 10,083,878
- Issue date Sep 25, 2018
- GLOBALFOUNDRIES Inc.
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device with decreased pitch contact to active regions
- Patent number 10,074,571
- Issue date Sep 11, 2018
- GLOBALFOUNDRIES INC.
- Brian J. Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with integrated passive structures
- Patent number 10,032,862
- Issue date Jul 24, 2018
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 9,922,831
- Issue date Mar 20, 2018
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 9,859,122
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-K dielectric for reducing gate induced drain leakage
- Patent number 9,837,319
- Issue date Dec 5, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to control fin tip placement
- Patent number 9,812,324
- Issue date Nov 7, 2017
- GLOBALFOUNDRIES Inc.
- Lei Zhuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect structure for semiconductor devices with multiple powe...
- Patent number 9,812,396
- Issue date Nov 7, 2017
- GLOBALFOUNDRIES Inc.
- Jason Eugene Stephens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming ANA regions in an integrated circuit
- Patent number 9,786,545
- Issue date Oct 10, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with integrated passive structures
- Patent number 9,768,195
- Issue date Sep 19, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-K dielectric for reducing gate induced drain leakage
- Patent number 9,768,071
- Issue date Sep 19, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 9,721,843
- Issue date Aug 1, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with integrated passive structures
- Patent number 9,698,159
- Issue date Jul 4, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 9,685,379
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with integrated passive structures
- Patent number 9,659,961
- Issue date May 23, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-K dielectric for reducing gate induced drain leakage
- Patent number 9,577,061
- Issue date Feb 21, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-K dielectric for reducing gate induced drain leakage
- Patent number 9,570,354
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 9,559,010
- Issue date Jan 31, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric high-k dielectric for reducing gate induced drain leakage
- Patent number 9,543,213
- Issue date Jan 10, 2017
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation structure having a nitride plug
- Patent number 9,443,929
- Issue date Sep 13, 2016
- International Business Machines Corporation
- Byeong Y. Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Merged source drain epitaxy
- Patent number 9,437,496
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES Inc.
- Michael P. Chudzik
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PASS-THROUGH STRUCTURES
- Publication number 20250212482
- Publication date Jun 26, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND AND FORKSHEET DEVICE ARCHITECTURE IN STANDARD CELLS
- Publication number 20250210519
- Publication date Jun 26, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SOURCE/DRAIN EPITAXIAL STRUCTURE FOR DIRECT BACKSIDE CONTACT
- Publication number 20250212457
- Publication date Jun 26, 2025
- QUALCOMM Incorporated
- Yan SUN
Information Patent Application
FORKSHEET DEVICE ARCHITECTURE IN STANDARD CELLS
- Publication number 20250212481
- Publication date Jun 26, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE DEEP RECESS SOURCE/DRAIN STRUCTURE FOR DIRECT BACKSIDE PO...
- Publication number 20250212513
- Publication date Jun 26, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
Information Patent Application
COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS WITH DIRECT V...
- Publication number 20250151386
- Publication date May 8, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
Information Patent Application
MEMORY CELL STRUCTURES USING BACKSIDE METAL CROSS-COUPLE STRUCTURES
- Publication number 20250151253
- Publication date May 8, 2025
- QUALCOMM Incorporated
- Yan SUN
Information Patent Application
GATE-TIE-DOWN IN BACKSIDE POWER ARCHITECTURE USING TRENCH-TIE-DOWN...
- Publication number 20250098301
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Deepak SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-TIE-DOWN IN BACKSIDE POWER ARCHITECTURE USING CONTACT JUMPER A...
- Publication number 20250098204
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Deepak SHARMA
Information Patent Application
SELF-ALIGNED BACKSIDE INTERCONNECT
- Publication number 20250098256
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Yan SUN
Information Patent Application
COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS WITH VERTICAL...
- Publication number 20250098221
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
Information Patent Application
MEMORY CELL STRUCTURES USING FULL BACKSIDE CONNECTIVITY
- Publication number 20250096075
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPACT LOGIC CELLS USING FULL BACKSIDE CONNECTIVITY
- Publication number 20250098302
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
Information Patent Application
GATE-ALL-AROUND FIELD EFFECT TRANSISTOR STRUCTURES
- Publication number 20250098217
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Yan SUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHODS F...
- Publication number 20250098220
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
Information Patent Application
BACKSIDE BI-DIRECTIONAL INTERCONNECT
- Publication number 20250098267
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Yan SUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND FIELD EFFECT TRANSISTOR STRUCTURES
- Publication number 20250096130
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Shreesh NARASIMHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VARIABLE VERTICAL-STACK NANOSHEET FOR GATE-ALL-AROUND DEVICES
- Publication number 20240429236
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Shreesh Narasimha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND (GAA) FIELD-EFFECT TRANSISTOR (FET) DEVICE HAVING F...
- Publication number 20240429300
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Shreesh Narasimha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES WITH DIFFERENT GATE DIELECTRIC THICKNESSES
- Publication number 20240421209
- Publication date Dec 19, 2024
- QUALCOMM Incorporated
- Shreesh Narasimha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED-SHAPED EXTENSION REGION(S) FOR GATE-ALL-AROUND (GAA) FIELD...
- Publication number 20240371924
- Publication date Nov 7, 2024
- QUALCOMM Incorporated
- Peijie Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING INTERCONNECT WITHOUT GATE CUT ISOLATION BLOCKING OPENING FO...
- Publication number 20210028067
- Publication date Jan 28, 2021
- GLOBALFOUNDRIES INC.
- Daniel J. Jaeger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
- Publication number 20200365702
- Publication date Nov 19, 2020
- Tessera, Inc.
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH SELF-ALIGNED AND NON-SELF-ALIGNED CON...
- Publication number 20200335591
- Publication date Oct 22, 2020
- GLOBALFOUNDRIES INC.
- Michael Aquilino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
- Publication number 20200027779
- Publication date Jan 23, 2020
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
- Publication number 20190296120
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Anthony I. CHOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
- Publication number 20190181037
- Publication date Jun 13, 2019
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
- Publication number 20180277424
- Publication date Sep 27, 2018
- International Business Machines Corporation
- Anthony I. Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH DECREASED PITCH CONTACT TO ACTIVE REGIONS
- Publication number 20180261512
- Publication date Sep 13, 2018
- GLOBALFOUNDRIES INC.
- Brian J. GREENE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BUFFER LAYER TO INHIBIT WORMHOLES IN SEMICONDUCTOR FABRICATION
- Publication number 20180197734
- Publication date Jul 12, 2018
- GLOBALFOUNDRIES INC.
- Bhupesh CHANDRA
- H01 - BASIC ELECTRIC ELEMENTS

Shreesh Narasimha

Person

Patents Grantslast 30 patents

Asymmetric high-k dielectric for reducing gate induced drain leakage

Forming interconnect without gate cut isolation blocking opening fo...

Field-effect transistors with self-aligned and non-self-aligned con...

Asymmetric high-k dielectric for reducing gate induced drain leakage

Semiconductor structure with integrated passive structures

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Semiconductor structure with integrated passive structures

Fin fabrication process with dual shallow trench isolation and tuna...

Device with decreased pitch contact to active regions

Semiconductor structure with integrated passive structures

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Methods to control fin tip placement

Interconnect structure for semiconductor devices with multiple powe...

Method of forming ANA regions in an integrated circuit

Semiconductor structure with integrated passive structures

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Semiconductor structure with integrated passive structures

Asymmetric high-k dielectric for reducing gate induced drain leakage

Semiconductor structure with integrated passive structures

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-K dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Asymmetric high-k dielectric for reducing gate induced drain leakage

Shallow trench isolation structure having a nitride plug

Merged source drain epitaxy

Patents Applicationslast 30 patents

PASS-THROUGH STRUCTURES

GATE-ALL-AROUND AND FORKSHEET DEVICE ARCHITECTURE IN STANDARD CELLS

RECESSED SOURCE/DRAIN EPITAXIAL STRUCTURE FOR DIRECT BACKSIDE CONTACT

FORKSHEET DEVICE ARCHITECTURE IN STANDARD CELLS

SELECTIVE DEEP RECESS SOURCE/DRAIN STRUCTURE FOR DIRECT BACKSIDE PO...

COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS WITH DIRECT V...

MEMORY CELL STRUCTURES USING BACKSIDE METAL CROSS-COUPLE STRUCTURES

GATE-TIE-DOWN IN BACKSIDE POWER ARCHITECTURE USING TRENCH-TIE-DOWN...

GATE-TIE-DOWN IN BACKSIDE POWER ARCHITECTURE USING CONTACT JUMPER A...

SELF-ALIGNED BACKSIDE INTERCONNECT

COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS WITH VERTICAL...

MEMORY CELL STRUCTURES USING FULL BACKSIDE CONNECTIVITY

COMPACT LOGIC CELLS USING FULL BACKSIDE CONNECTIVITY

GATE-ALL-AROUND FIELD EFFECT TRANSISTOR STRUCTURES

COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHODS F...

BACKSIDE BI-DIRECTIONAL INTERCONNECT

GATE-ALL-AROUND FIELD EFFECT TRANSISTOR STRUCTURES

VARIABLE VERTICAL-STACK NANOSHEET FOR GATE-ALL-AROUND DEVICES

GATE-ALL-AROUND (GAA) FIELD-EFFECT TRANSISTOR (FET) DEVICE HAVING F...

SEMICONDUCTOR DEVICES WITH DIFFERENT GATE DIELECTRIC THICKNESSES

ENHANCED-SHAPED EXTENSION REGION(S) FOR GATE-ALL-AROUND (GAA) FIELD...

FORMING INTERCONNECT WITHOUT GATE CUT ISOLATION BLOCKING OPENING FO...

ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE

FIELD-EFFECT TRANSISTORS WITH SELF-ALIGNED AND NON-SELF-ALIGNED CON...

SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE

SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES

DEVICE WITH DECREASED PITCH CONTACT TO ACTIVE REGIONS

BUFFER LAYER TO INHIBIT WORMHOLES IN SEMICONDUCTOR FABRICATION