Shui-Chin Huang

Person

Ben-Yuan St. Tainan, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Low thermal budget fabrication method for a mask read only memory d...
- Patent number 7,442,610
- Issue date Oct 28, 2008
- Macronix International Co., Ltd.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single-poly EEPROM
- Patent number 7,193,265
- Issue date Mar 20, 2007
- United Microelectronics Corp.
- Nai-Chen Peng
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming P-channel EEPROM
- Patent number 7,054,196
- Issue date May 30, 2006
- United Microelectronics Corp.
- Chien-Hung Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory and method of operation
- Patent number 6,977,869
- Issue date Dec 20, 2005
- United Microelectronics Corp.
- Shui-Chin Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having buried source/drain region and fabrication the...
- Patent number 6,831,335
- Issue date Dec 14, 2004
- Macronix International Co., Ltd.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating memory device having buried source/drain region and fab...
- Patent number 6,645,816
- Issue date Nov 11, 2003
- Macronix International Co., Ltd.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical read-only memory and fabrication thereof
- Patent number 6,617,633
- Issue date Sep 9, 2003
- Macronix International Co., Ltd.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method of a gate-split flash memory
- Patent number 6,589,842
- Issue date Jul 8, 2003
- Winbond Electronics Corporation
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a mask ROM with raised bit-line on each burie...
- Patent number 6,440,803
- Issue date Aug 27, 2002
- Macronix International Co., Ltd.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of integrating a salicide process and a self-aligned contact...
- Patent number 6,383,878
- Issue date May 7, 2002
- Winbond Electronics Corp.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contact process using stacked spacers
- Patent number 6,380,042
- Issue date Apr 30, 2002
- Winbond Electronics Corp.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing floating gate of flash memory
- Patent number 6,362,048
- Issue date Mar 26, 2002
- Winbond Electronics Corp.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SINGLE-POLY EEPROM
- Publication number 20060208306
- Publication date Sep 21, 2006
- Nai-Chen Peng
- G11 - INFORMATION STORAGE
Information Patent Application
Method of forming self aligned contact
- Publication number 20050153543
- Publication date Jul 14, 2005
- UNITED MICROELECTRONICS CORP.
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for programming P-channel EEPROM
- Publication number 20050116262
- Publication date Jun 2, 2005
- Chen-Hung Chen
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY AND METHOD OF OPERATION
- Publication number 20050111262
- Publication date May 26, 2005
- Shui-Chin Huang
- G11 - INFORMATION STORAGE
Information Patent Application
Low thermal budget fabrication method for a mask read only memory d...
- Publication number 20030207539
- Publication date Nov 6, 2003
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory device having buried source/drain region and fabrication the...
- Publication number 20030199142
- Publication date Oct 23, 2003
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL READ-ONLY MEMORY AND FABRICATION THEREOF
- Publication number 20030122171
- Publication date Jul 3, 2003
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE HAVING BURIED SOURCE/DRAIN REGION AND FABRICATION THE...
- Publication number 20030100158
- Publication date May 29, 2003
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Manufacturing method of a gate-split flash memory
- Publication number 20020068403
- Publication date Jun 6, 2002
- Winbond Electronics Corporation
- Shui-Chin Huang
- H01 - BASIC ELECTRIC ELEMENTS

Shui-Chin Huang

Person

Patents Grantslast 30 patents

Low thermal budget fabrication method for a mask read only memory d...

Single-poly EEPROM

Method for programming P-channel EEPROM

Non-volatile memory and method of operation

Memory device having buried source/drain region and fabrication the...

Fabricating memory device having buried source/drain region and fab...

Vertical read-only memory and fabrication thereof

Manufacturing method of a gate-split flash memory

Method of fabricating a mask ROM with raised bit-line on each burie...

Method of integrating a salicide process and a self-aligned contact...

Self-aligned contact process using stacked spacers

Method of manufacturing floating gate of flash memory

Patents Applicationslast 30 patents

SINGLE-POLY EEPROM

Method of forming self aligned contact

Method for programming P-channel EEPROM

NON-VOLATILE MEMORY AND METHOD OF OPERATION

Low thermal budget fabrication method for a mask read only memory d...

Memory device having buried source/drain region and fabrication the...

VERTICAL READ-ONLY MEMORY AND FABRICATION THEREOF

MEMORY DEVICE HAVING BURIED SOURCE/DRAIN REGION AND FABRICATION THE...

Manufacturing method of a gate-split flash memory