Shumay Dou

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of preventing resist poisoning in dual damascene structures
- Patent number 6,969,683
- Issue date Nov 29, 2005
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of preventing resist poisoning in dual damascene structures
- Patent number 6,713,386
- Issue date Mar 30, 2004
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of protecting acid-catalyzed photoresist from chip-generated...
- Patent number 6,458,508
- Issue date Oct 1, 2002
- LSI Logic Corporation
- Nicholas F. Pasch
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
System and method for performing optical proximity correction on th...
- Patent number 6,425,117
- Issue date Jul 23, 2002
- LSI Logic Corporation
- Nicholas F. Pasch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using PV...
- Patent number 6,239,499
- Issue date May 29, 2001
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using me...
- Patent number 6,157,087
- Issue date Dec 5, 2000
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using fi...
- Patent number 6,060,787
- Issue date May 9, 2000
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using fi...
- Patent number 5,981,352
- Issue date Nov 9, 1999
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using me...
- Patent number 5,966,613
- Issue date Oct 12, 1999
- LSI Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Consistent alignment mark profiles on semiconductor wafers using PV...
- Patent number 5,926,720
- Issue date Jul 20, 1999
- LSI Logic Corporation
- Joe W. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment mark contrast enhancement
- Patent number 5,863,825
- Issue date Jan 26, 1999
- LSI Logic Corporation
- Nicholas F. Pasch
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method of preventing resist poisoning in dual damascene structures
- Publication number 20040161927
- Publication date Aug 19, 2004
- LSI Logic Corporation
- Rongxiang Hu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Method of preventing resist poisoning in dual damascene structures

Method of preventing resist poisoning in dual damascene structures

Method of protecting acid-catalyzed photoresist from chip-generated...

System and method for performing optical proximity correction on th...

Consistent alignment mark profiles on semiconductor wafers using PV...

Consistent alignment mark profiles on semiconductor wafers using me...

Consistent alignment mark profiles on semiconductor wafers using fi...

Consistent alignment mark profiles on semiconductor wafers using fi...

Consistent alignment mark profiles on semiconductor wafers using me...

Consistent alignment mark profiles on semiconductor wafers using PV...

Alignment mark contrast enhancement

Patents Applicationslast 30 patents

Method of preventing resist poisoning in dual damascene structures