Siddesh Halavarthi Math Revana

Person

Bangalore, IN

People

Patents Applicationslast 30 patents

Information Patent Application
REDUCING PROCESSOR POWER CONSUMPTION
- Publication number 20210157380
- Publication date May 27, 2021
- QUALCOMM Incorporated
- Anubha MOTWANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE FLUSH ABORT CONTROLLER SYSTEM AND METHOD
- Publication number 20200285584
- Publication date Sep 10, 2020
- QUALCOMM Incorporated
- Raghavendra Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMAL CACHE RETENTION MECHANISM
- Publication number 20200264788
- Publication date Aug 20, 2020
- QUALCOMM Incorporated
- Raghavendra SRINIVAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRESSIVE POWER-UP SCHEME FOR CACHES BASED ON OCCUPANCY STATE
- Publication number 20190332166
- Publication date Oct 31, 2019
- QUALCOMM Incorporated
- Siddesh Halavarthi Math Revana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING INTERRUPT SERVICE ROUTINE (ISR) PREFETCHING IN MULTICORE...
- Publication number 20190324932
- Publication date Oct 24, 2019
- QUALCOMM Incorporated
- Raghavendra Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT
- Publication number 20190073323
- Publication date Mar 7, 2019
- QUALCOMM Incorporated
- Siddesh Halavarthi Math Revana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING PRIVATE CACHE ALLOCATION FOR POWER-COLLAPSED PROCESSOR CO...
- Publication number 20190065372
- Publication date Feb 28, 2019
- QUALCOMM Incorporated
- Kaustav Roychowdhury
- G06 - COMPUTING CALCULATING COUNTING

Siddesh Halavarthi Math Revana

Person

Patents Applicationslast 30 patents

REDUCING PROCESSOR POWER CONSUMPTION

CACHE FLUSH ABORT CONTROLLER SYSTEM AND METHOD

OPTIMAL CACHE RETENTION MECHANISM

PROGRESSIVE POWER-UP SCHEME FOR CACHES BASED ON OCCUPANCY STATE

PROVIDING INTERRUPT SERVICE ROUTINE (ISR) PREFETCHING IN MULTICORE...

BUFFERING TRANSACTION REQUESTS TO A SUBSYSTEM VIA A BUS INTERCONNECT

PROVIDING PRIVATE CACHE ALLOCATION FOR POWER-COLLAPSED PROCESSOR CO...