Siddharth RAVICHANDRAN

Person

Austin, TX, US

People

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Package with Integrated Capacitors
- Publication number 20250015019
- Publication date Jan 9, 2025
- Chipletz, Inc.
- Michael SU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low-Equivalent-Series-Resistance Capacitors with Solid-State Curren...
- Publication number 20240258041
- Publication date Aug 1, 2024
- Chipletz, Inc.
- Siddharth Ravichandran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Prevention, Cessation, Detection, and Moni...
- Publication number 20240120293
- Publication date Apr 11, 2024
- Chipletz, Inc.
- Michael Su
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package Assembly and Method of Attaching Multi-Height Dies/Modules...
- Publication number 20230411174
- Publication date Dec 21, 2023
- Chipletz, Inc.
- Michael Su
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Inductors Embedded in Package Substrate and Board and Method and Sy...
- Publication number 20230395305
- Publication date Dec 7, 2023
- Chipletz, Inc.
- Siddharth Ravichandran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Through Package Vertical Interconnect and Method of Making Same
- Publication number 20230343687
- Publication date Oct 26, 2023
- Chipletz, Inc.
- Bryan Black
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH INTEGRATED CAPACITORS
- Publication number 20230290746
- Publication date Sep 14, 2023
- CHIPLETZ, INC.
- Michael SU
- H01 - BASIC ELECTRIC ELEMENTS

Siddharth RAVICHANDRAN

Person

Patents Applicationslast 30 patents

Semiconductor Package with Integrated Capacitors

Low-Equivalent-Series-Resistance Capacitors with Solid-State Curren...

Method and Apparatus for Prevention, Cessation, Detection, and Moni...

Package Assembly and Method of Attaching Multi-Height Dies/Modules...

Inductors Embedded in Package Substrate and Board and Method and Sy...

Through Package Vertical Interconnect and Method of Making Same

SEMICONDUCTOR PACKAGE WITH INTEGRATED CAPACITORS