Patent Application
20230411174
The present invention is directed in general to integrated circuit packages and methods of manufacturing same. In one aspect, the present invention relates to an integrated circuit package assembly with multiple integrated circuit dies or modules attached together on an interposer or substrate.
Due to the increasing cost and complexity for manufacturing integrated chips with higher density requirements that are running up against lithographic reticle limits, there are increasingly practical ceilings on how large an integrated circuit die can be manufactured. Another manufacturing challenge is the increasing difficulty in integrating disparate functional blocks using different transistors nodes and backend of line copper interconnect schemes on a single integrated circuit chip. In addition, increasing device density means that a single defect on a single IC chip can dramatically reduce the overall yield of the wafer used to manufacture the IC chip. One promising solution to improve yield and performance with reduced cost is to divide the overall circuit functionality among multiple smaller integrated circuits (or chiplets) having specialized functions. With this approach, the separate testing of the individual chiplets will result in smaller amount of silicon being rejected as defective than would be the case if the combined functionality were manufactured in a single chip, assuming a uniform fault distribution rate. However, this approach also requires extensive technical challenges with interconnecting multiple chiplets together, including longer signal routing paths with potentially higher losses, lower available bandwidth, higher power consumption and/or higher latency. Additional interconnect complications arise with different voltages, timing requirements, and protocols used by the chiplets, all of which make chiplets look like a less obvious approach.
One solution for addressing these challenges is to connect the chiplets into a single semiconductor package substrate, such as a common interposer or substrate, so that individually tested chiplets can be reassembled and packaged into a complete final SoC, thereby yielding a significantly larger number of functional SoCs. Such assemblies are referred to as System-in-Package (SiP) assemblies. An example of such a semiconductor package substrate is described in U.S. patent application Ser. No. 17/692587 entitled “Semiconductor Package with Integrated Circuits” which was filed on Mar. 11, 2022, and which is incorporated herein by reference in its entirety as if fully set forth herein. The single semiconductor package substrate may be embodied as a silicon interposer or substrate having embedded passive or active components, such as a network of thin-film capacitors provided for vertical power delivery in a package where the capacitors are embedded in the package substrate core, thereby facilitating the connection of multiple ICs in a single package for critical AI workloads, immersive consumer experiences, and high-performance computing. While existing WLP approaches can provide interconnects between die pads with <50 um pitch and solder balls with ˜0.5 mm pitch, there are processing costs and design constraints which constrain the ability of existing bumping technology solutions to achieve finer pitches while meeting the applicable performance, design, complexity and cost constraints for packing integrated circuit devices.
As will be appreciated, SiP assemblies have several advantages over a System-on-Chip (SoC), including the ability to combine many different IC chips (e.g., analog, digital, and radio frequency (RF) dice) in the same package, where each die is implemented using that domain's most appropriate technology process. Also, designers can employ a number of off-the-shelf dice coupled, perhaps, with a limited number of relatively small, internally-developed components. However, there are also challenges with combining disparate chips into a single packaged assembly since the individual die will often have different lateral and vertical dimensions, differing heat dissipation requirements, different pitch spacing requirements, etc. As a result, the existing solutions for providing SiP assemblies are extremely difficult at a practical level.
The present invention may be understood, and its numerous objects, features and advantages obtained, when the following detailed description is considered in conjunction with the following drawings.
An integrated circuit package assembly and associated method of fabrication are disclosed for forming an integrated circuit package assembly with an encapsulated plurality of integrated circuit dice or chip modules attached to a package substrate with embedded active and/or passive circuit elements or devices and also attached to a heat sink lid/cover that is formed on and thermally connected to the encapsulated integrated circuit dice/chip modules with one or more thermal conductive layers to contact the integrated circuit dice/chip modules and the package substrate, thereby enabling removal of heat from the integrated circuit dice/chip modules and the embedded circuit elements in the package substrate. In selected die-level reconstitution embodiments, a plurality of multi-height integrated circuit dice or chip modules are attached to a first temporary carrier and encapsulated with a molding compound which is then grinded to expose the integrated circuit dice or chip modules at a flat heat dissipation surface, and then the encapsulated and grinded integrated circuit dice or chip modules are transferred to a second temporary carrier to form an assembly interface of interconnect conductor structures (e.g., microbumps, C4 bumps, solder balls, Cu—Cu joint, Nano sintered silver or Cu, etc.) on the integrated circuit dice or chip modules before being transferred to a dicing tape for singulation into individual modules which may be attached to a package substrate with embedded active and/or passive circuit elements so that a heat sink lid/cover can be formed with one or more thermal conductive layers to contact at least the exposed integrated circuit dice/chip modules. In other die-level reconstitution embodiments, a plurality of multi-height integrated circuit dice or chip modules having an assembly interface of interconnect conductor structures are attached to a temporary carrier and encapsulated with a molding compound which is then grinded to expose the integrated circuit dice or chip modules at a flat heat dissipation surface, and then the encapsulated and grinded integrated circuit dice or chip modules are transferred to a dicing tape for singulation into individual modules which may be attached to a package substrate with embedded active and/or passive circuit elements so that a heat sink lid/cover can be formed with one or more thermal conductive layers to contact at least the exposed integrated circuit dice/chip modules. In other die-level reconstitution embodiments, each grouping of multi-height integrated circuit dice/chip modules may be surrounded by a thermally conductive stiffener ring when mounted to the carrier or package substrate(s) before performing the mold compound encapsulation and grinding so that a thermally conductive heat sink lid/cover is formed to contact each of the exposed IC dice/chip modules and the embedded active and/or passive circuit elements in the package substrate(s) through the stiffener ring.
In selected substrate-level reconstitution embodiments, a panel of package substrates with embedded active and/or passive circuit elements are attached to a temporary carrier and then a plurality of multi-height integrated circuit dice or chip modules with an assembly interface of interconnect conductor structures are attached to each of the package substrates and encapsulated with a molding compound which is then grinded to expose the integrated circuit dice or chip modules at a flat heat dissipation surface, and then the encapsulated and grinded panel of integrated circuit dice or chip modules are transferred to a dicing tape for singulation into individual modules which may be attached to a heat sink lid/cover with one or more thermal conductive layers to contact at least the exposed integrated circuit dice/chip modules. In other selected substrate-level reconstitution embodiments, the integrated circuit package assembly may be formed by attaching a panel of multi-height integrated circuit dice/chip modules and a thermally conductive, surrounding stiffener ring to one or more carrier-mounted package substrates having embedded active and/or passive circuit elements, encapsulating the panel in a molding compound to cover the multi-height IC die/chip modules and stiffener ring, grinding the molding compound down to expose the IC dice/chip modules and surrounding stiffener ring at a uniform height, and then forming a heat sink lid/cover with one or more thermal conductive layers to contact each of the exposed IC dice/chip modules and the embedded active and/or passive circuit elements in the package substrate(s) through the stiffener ring, and then singulating the encapsulated panel/package substrate(s) into individual integrated circuit package assemblies. As will be appreciated, the singulation process may use a cut line or dicing line that extends through the substrate, or just through the molding compound between two substrates, and the cut line may be flushed to the molded stiffener, or the molded stiffener may be recessed from the cut line
In selected warpage-correcting embodiments, a warped package substrate with conductive landing pads is processed to selectively form one or more conductive landing pad extension layers on the conductive landing pads (e.g., on the periphery or in the center or with a combination or in concentric bands) prior to attaching individual integrated circuit dice or chip modules to the warped package substrate. As disclosed herein, the landing pad extension layer(s) may be formed with any suitable conductive material, including but not limited to solder, Cu paste, Ag paste, metal, metal alloy, direct metal-to-metal bonding, thermal paste, thermal pad, etc. By properly placing the location of the selectively formed additional landing pad extension layer(s) on the conductive landing pads of the warped package substrate, solid electro-physical connections are established between the conductive landing pads and the assembly interface of interconnect conductor structures on each IC die/chip module. In other warpage-correcting embodiments, a warped package substrate may include one or more magnetic stiffener rings or elements formed on the package substrate, either before or after attaching the IC dice/chip modules to the warped package substrate. By properly locating the magnetic stiffener rings or elements, the warped package substrate may be de-warped or straightened during assembly by temporarily or permanently magnetizing the magnetic stiffener rings or elements with a magnetic chuck table or other suitable magnetic field generator, thereby straightening out the package substrate during assembly.
Various illustrative embodiments will now be described in detail with reference to the accompanying figures. While various details are set forth in the following description, it will be appreciated that the present invention may be practiced without these specific details, and that numerous implementation-specific decisions may be made to the invention described herein to achieve the device designer's specific goals, such as compliance with process technology or design-related constraints, which will vary from one implementation to another. While such a development effort might be complex and time-consuming, it would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. For example, selected aspects are depicted with reference to simplified cross sectional drawings of a package assembly without including every device feature or geometry in order to avoid limiting or obscuring the present invention. It is also noted that, throughout this detailed description, certain materials will be formed and removed to fabricate the package assembly structure. Where the specific procedures for forming or removing such materials are not detailed below, conventional techniques to one skilled in the art for growing, depositing, removing or otherwise forming such layers at appropriate thicknesses shall be intended. Such details are well known and not considered necessary to teach one skilled in the art of how to make or use the present invention.
Turning now to
To support and enable electrical connection between the die/chip modules 35, 36 and the printed circuit board 10, the package substrate 12-26 includes a substrate core 15 that is formed with an insulating material (e.g., plastic and/or fiberglass) that is sandwiched between first and second redistribution line (RDL) stacks 25-26, 13-14. In the substrate core 15, one or more embedded active and/or passive modules 21-24 are formed. As illustrated, a plurality of embedded active and/or passive modules 21-24 may be separately formed in separate cavities of the substrate core 15 to be isolated from one another by an intervening insulation layer 25, but in other embodiments, the embedded active and/or passive modules 21-24 may be formed in a single continuous cavity of the substrate core 15.
As depicted, the embedded active and/or passive modules 21-24 may include a variety of different circuit components may take any suitable form, shape, size, thickness, or structure. In addition, one or more of the embedded active and/or passive modules 21-24 can be positioned in alignment with an outline or power domain of an IC die/chip module 35, 36. For example, there may be design and performance benefits from aligning the position of one or more surface attachable devices (e.g., die/module 35) so that has a “shadow” within which the underlying embedded circuit components (e.g., capacitors) C117 and C218) are located. As a result, each embedded circuit component can follow the physical layout or profile of each domain/functional block of a single surface attachable device. While one or more embedded circuit components can be positioned to service a single surface attachable device under its shadow, the connections between the capacitors and surface attachable devices through the package RDL stack 26 can also allow an embedded circuit component to service multiple surface attachable devices.
By way of providing examples of different embedded circuit components, the first embedded module 21 is depicted as including a first vertical planar capacitor Cl 17 which may be, for example, a power delivery capacitor. As depicted with the enlarged image of the embedded component 21, the capacitor C117 that is embedded in the substrate core 15 includes a pair of capacitor plates formed from the conductive via structures 16 which are separated by a capacitor dielectric 27. In addition, the second embedded module 22 is depicted as including a second vertical multi-layer capacitor C218. As depicted with the enlarged image of the embedded component 22, the capacitor C218 that is embedded in the substrate core 15 is constructed with sandwiched capacitor plate layers 18 including interleaved conductive fingers 28 which are attached to the conductive via structures 16 and separated by a capacitor dielectric 29. Thus, it will be appreciated that any suitable capacitor can be embedded, including a multi-layer ceramic capacitor (MLCC), thin-film based (Al, Ta, etc.), polymer-cap, etc., and can include a combination of different types of capacitors for different voltages (1.2 V, 5V, 100V depending on the capacitor), frequencies, and densities. To provide another example of an embedded circuit component, the third embedded module 23 is depicted as including a third active circuit component A319, which may include an integrated circuit die for implementing a specified power, RF, digital and/or photonic functionality, such as filtering power noise, converting and/or regulating regulate voltage, assisting with die-to-die communication, etc. And to provide another example of an embedded circuit component, the fourth embedded module 24 is depicted as including a fourth passive circuit component P420, which may include any type of passive component, such as a capacitor, resistor, inductor, etc.
By forming at least a portion of the substrate core 15 with embedded capacitor(s), at least some of the vertical connections in the first and second RDL stacks 26, 14 can connect the capacitor(s) to the external circuitry on the PCB 10 and at least one of the attachable IC die/chip modules 35, 36 for filtering AC noise from the DC power. Moreover, embedding or forming the substrate core 15 with the capacitor(s) and providing vertical delivery of DC power through the capacitor(s) avoids RC signal delays and poor device density resulting from the use of decoupling capacitors having terminals on left and right sides for lateral power delivery and signal routing through the capacitor or placement of the capacitor on the surface of the package.
The substrate core 15 also includes one or more defined conductive signal or power via elements 16 to provide electrical and/or thermal conductive paths to and from the substrate core 15 and the embedded active and/or passive modules 21-24. The conductive signal or power via elements 16 may be formed as conductive via structures which extend through the substrate core 15 and which have top and bottom terminal landing pads. At least one of the conductive via elements 16 is provided for vertically passing DC power from the external circuitry 10 to one or more of the die/chip modules 35, 36, either directly or through one of the embedded active/passive modules 21-24 (e.g., capacitor C1). In selected embodiments, each conductive signal or power via element 16 may be embodied as a plated-through hole (PTHs).
On a first or top surface of the substrate core 15, the package substrate 12-26 includes a first redistribution line (RDL) stack of conductive elements 26 formed in one or more first insulator layer(s) 25 to connect the set of first level interconnects 33 to the defined conductive signal or power via elements 16 and embedded active and/or passive modules 21-24. When used for interconnecting to the IC die/chip modules 35, 36, the first RDL stack 26 may have fine-pitch routing layers. In addition, one or more fine-pitch IC wiring lines 34 can also be provided in the first RDL stack for signaling between the die/chip modules 35, 36. And on a second or bottom surface of the substrate core 15, the package substrate 12-26 includes a second RDL stack of conductive elements 14 formed in one or more second insulator layer(s) 13 to connect the set of second level interconnects 11 to the defined conductive signal or power via elements 16 and embedded active and/or passive modules 21-24. When used for interconnecting to the second level interconnects 11, the second RDL stack 14 may have a few course-pitch routing layers for power or I/O connections to the PCB 10. With the RDL stacks 26, 14, the conductive elements 16, 21-24 in the substrate core 15 are extended to make electrical contact, respectively, with the first and second level interconnects 33, 11, thereby forming interconnections than can be accommodated by the individual die size of the IC die/chip modules 35, 36. As a result of the configurations of the first and second RDL stacks 26, 14, terminal metals can be extremely close to each other, allowing small pitch first level interconnect microbumps 33 (e.g., 80 micron pitch) to vertically align with second level interconnect solder balls 11 without laterally routing of DC power lines through the RDL stacks 14, 26.
As will be appreciated, the die/module devices 35, 36 can be integrated circuit devices, integrated passive devices, microelectromechanical systems (MEMS). However, when different die/chip module devices 35, 36 having different heights are attached to the package substrate 12-26, this results in a number of packaging and performance challenges. For example, when the IC die/chip module 35 is shorter than the IC die/module 36, the different heights cause non-planar encapsulation profiles which can adversely affect chip handling, assembly, and placement. Another packaging and performance challenge resulting from having multi-height IC die/chip modules 35, 36 is that there is uneven thermal dissipation and heat transfer from the die/module devices 35, 36 since conventionally formed heat sink lid/covers are not in direct thermal contact with the IC die/chip modules 35, 36 due to their differing heights.
To illustrate an example sequence of process steps for fabricating an integrated circuit package assembly in accordance with selected die-level reconstitution embodiments of the present disclosure, reference is now made to
As depicted in
As illustrated, the multi-chip package substrate 119 is similar to the multi-chip package substrate 12-26 depicted in
To ensure that the plurality of IC dice or chip modules 101-103, 120 make direct thermal contact to the heat spreader lid 133 via the TIM and BSM layers 130, 131, the vertical or height dimensions of the interior cavity space in the head spreader lid 133 are controlled or specified to be equal to, or slightly less than, the combined height of the interconnect conductors 113, the IC dice or chip modules 101-103, 120, the BSM layer 130, and the TIM layer 131. And by using a compressible or compliant TIM layer(s) 131, 132, the exertion of downward clamp force to compress the heat spreader lid 133 against the multi-chip substrate 119 causes the IC dice or chip modules 101-103, 120 to make direct thermal contact with the heat spreader lid 133 without exerting excessive compression forces that could damage or crack the IC dice or chip modules 101-103, 120. The use of a compressible or compliant TIM layer(s) 131, 132 also effectively absorbs thickness variability in the package assembly components.
To illustrate an example sequence of process steps for fabricating an integrated circuit package assembly in accordance with selected second die-level reconstitution embodiments of the present disclosure, reference is now made to
As depicted in
As illustrated, the multi-chip package substrate 230 is similar to the multi-chip package substrate 12-26 depicted in
Though not shown, it will be appreciated that additional processing may be applied to attach or mount a heat spreader lid or heat sink cover on the package assembly similar to the embodiment illustrated in
To illustrate an example sequence of process steps for fabricating an integrated circuit package assembly in accordance with selected substrate-level reconstitution embodiments of the present disclosure, reference is now made to
As depicted in
After attaching the multi-chip package substrates 402, 403 to the substrate carrier 401, an optional molding compound material 404 may be applied to help secure the multi-chip package substrates 402, 403. In selected embodiments, the step for forming the molding compound material 404 may be omitted or replaced by a subsequent molding compound formation step. The molding compound material 404 can be any appropriate encapsulant having properties that are suitable for providing mechanical support and structural integrity to maintain the physical arrangement of the multi-chip package substrates 402, 403 on the carrier 401, including during the subsequent grinding or etching process (described below). As will be appreciated, the molding compound material 404 may use any suitable molding material (e.g., silica-filled epoxy molding compounds, plastic encapsulation resins, and other polymeric materials such as silicones, polyimides, phenolics, and polyurethanes), and may be applied by a variety of standard processing techniques used in encapsulation including, for example, printing, pressure molding, injection molding, film-assisted molding, and spin application. In selected embodiments, the molding compound material 404 is formed to a height that is at or below the height of the multi-chip package substrates 402, 403, or may be formed to completely cover the multi-chip package substrates 402, 403, followed by etching or grinding to planarize the molding compound material 404 with the multi-chip package substrates 402, 403. Once the molding compound material 404 is applied, the panel can be cured by exposing the materials to certain temperatures for a period of time, or by applying curing agents, or both.
Before or after attaching the integrated circuit dice 410-417 to the multi-chip package substrates 402, 403, one or more optional stiffener structures 418, 419 may be formed on each of the multi-chip package substrates 402, 403 to surround or encircle the integrated circuit dice 410-417. The stiffener structures 418, 419 can be formed with any suitable material having structural properties that are suitable for providing mechanical support and structural integrity to reduce any warpage or bending of the multi-chip package substrates 402, 403. In addition, the material properties of the stiffener structures 418, 419 may include thermal conductive properties to enable the stiffener structures 418, 419 to provide a thermal conduction or heat spreading path for heat generated by the integrated circuit dice 410-417 and/or embedded elements in the multi-chip package substrates 402, 403. As depicted, the stiffener structures 418, 419 may be formed to include a thermally conductive adhesive layer 418A, 419A which is used to attach the stiffener structures 418, 419 to one or more thermal conduction paths 405-408 formed in the multi-chip package substrates 402, 403. For example, the thermally conductive adhesive layers 418A, 419A may be a TIM film or tape and applied to the bottom surface of each stiffener structure 418, 419.
In selected embodiments, each stiffener structure (e.g., 418) is formed as a ringed structure that surrounds the integrated circuit dice (e.g., 410-413) formed in a package substrate (e.g., 402). In other selected embodiments where the stiffener structures 418, 419 provide a thermal conduction path for heat generated by the integrated circuit dice 410-417 and/or embedded elements in the multi-chip package substrates 402, 403, the height of each stiffener structure (e.g., 418) is at least as tall as the shortest integrated circuit die (e.g., 412). In other embodiments where the stiffener structures 418, 419 do not provide a thermal conduction path, the height of each stiffener structure (e.g., 418) may be shorter than any of the dice. In other embodiments, the step for forming the stiffener structures 418, 419 may be omitted.
As disclosed herein, a plurality of multi-height integrated circuit dice are reconstituted or attached to a multi-chip package substrate using any suitable die attach mechanism, either before or after encapsulating and planarizing the multi-height integrated circuit dice in a molding compound structure which exposes a flat heat dissipation surface of the etched or grinded integrated circuit dice. In embodiments where the planarized integrated circuit dice are surrounded with a stiffener ring structure and encapsulated with a molding compound, the resulting module(s) of encapsulated dice should have sufficient structural integrity to maintain a substantially flat or planar positioning relative to one another. As a result, the assembly interface connectors (e.g., microbump conductors, solder, Cu joint, etc.) formed on the active surfaces of the planarized integrated circuit dice are also substantially flat or planar in their relative positioning. However, certain types of device packaging structures, such as multi-chip package substrates, can be warped due to differing stress performance of the materials used to form the device packaging structures. The resulting warpage can prevent assembly interface connectors on the encapsulated dice module from forming a solid electro-physical connection with the terminal metals of the RDL stack in the multi-chip package substrate.
To address the challenge of connecting dice to a warped package substrate, selected embodiments of the present disclosure provide a method and apparatus for addressing package substrate warpage by selectively extending the substrate landing pad heights in localized areas of a warped substrate to effectively planarize the substrate landing pads, thereby mitigating the non-contact between the assembly interface connectors and the substrate landing pads caused by substrate warpage during assembly. For an improved understanding of selected embodiments of the present disclosure, reference is now made to
By selective adding edge solder layers 503 (or similar conductive contact materials) to selected substrate landing pads 502 located on peripheral edges of the warped multi-chip substrate 501, different substrate landing pad heights are effectively produced at the edges of the warped substrate. As will be appreciated, the thickness of the edge solder layers 503 may be selectively varied across the surface of the warped substate to account for warpage-induced gaps between the first level interconnect conductors 516 (e.g., bumps) at the substrate landing pads 502. In this way, the “taller” substrate landing pads (formed with the substrate landing pads 502 and the edge solder layers 503) at the edges are positioned to make contact with the attached first level interconnect conductors 516 (e.g., bumps) at the edges, while the “shorter” substrate landing pads (formed only with the substrate landing pads 502) are also positioned to make contact with the attached first level interconnect conductors 516 (e.g., bumps) at the center. In effect, a “taller” edge substrate landing pads 502/503 compensate for the positive warpage in the substrate 501.
As will be appreciated, the device packaging structures may have other warpage effects that can prevent assembly interface connectors on the encapsulated dice module from forming a solid electro-physical connection with the terminal metals of the RDL stack in the multi-chip package substrate. For example, reference is now made to
By selective adding edge solder layers 603 (or similar conductive contact materials) to selected substrate landing pads 602 located on central area of the warped multi-chip substrate 601, different substrate landing pad heights are effectively produced at the center of the warped substrate. As will be appreciated, the thickness of the center solder layers 603 may be selectively varied across the surface of the warped sub state to account for warpage-induced gaps between the first level interconnect conductors 616 (e.g., bumps) at the substrate landing pads 602. In this way, the “taller” substrate landing pads (formed with the substrate landing pads 602 and the edge solder layers 603) at the center are positioned to make contact with the attached first level interconnect conductors 616 (e.g., bumps) at the edges, while the “shorter” substrate landing pads (formed only with the substrate landing pads 602) are also positioned to make contact with the attached first level interconnect conductors 616 (e.g., bumps) at the peripheral edges. In effect, a “taller” center substrate landing pads 602/603 compensate for the negative warpage in the substrate 601.
As disclosed herein with respect to
As disclosed herein, the challenge of connecting IC dice to a warped package substrate can also be addressed by providing a method and apparatus wherein a magnetic stiffener ring is formed on the warped package substrate and then applying magnetic field which interacts with the magnetic stiffener ring to clamp the warped package substrate into a straighten or non-warped shape, thereby mitigating the non-contact between assembly interface connectors on the IC dice and the substrate landing pads caused by substrate warpage during assembly. For example, reference is now made to
As depicted in
In selected embodiments, the magnetic stiffener rings 710, 715 are attached to the substrate 703 and positioned to leave a space where the IC die 711-714 will subsequently be placed on the substrate 703 (e.g., after clamping or straightening of the substrate). In other embodiments, the magnetic stiffener rings 710, 715 are attached to the substrate 703 at the same time or after attaching the IC die 711-714 to the substrate 703. In any case, the magnetic stiffener rings 710, 715 are formed with a suitable magnetic material having ferromagnetic, ferrimagnetic, or paramagnetic properties which will respond to a magnetic field 702 to exert a physical clamping force on the warped package substrate 703 to clamp the warped package substrate 703 into a straighten or non-warped shape. As a result there are non-contacts or gaps between the first level interconnect conductors 616 (e.g., bumps) and the substrate landing pads 602 on at least the central regions of the multi-chip package substrate 601. The non-contact or gap effect can be further pronounced with first level interconnect conductors 616 which implement finer bump pitches since smaller amounts of solder volume are used.
Referring now to
Turning now to
At step 83, a stiffener ring or other structure may optionally be attached to the carrier to surround the multi-height integrated circuit components. In selected embodiments, the stiffener element(s) may be attached to the carrier substrate by using a thermally conductive adhesive material, such as a patterned thermal interface material (TIM) layer formed on the carrier. In other embodiments, the stiffener element(s) may be formed with a thermal interface material. In other embodiments, the stiffener element(s) may be formed with a magnetic material having ferromagnetic, ferrimagnetic, or paramagnetic properties which will respond to a magnetic field. The height of the stiffener elements may be shorter than the shortest integrated circuit component and still provide mechanical stiffening benefits, but may also be taller than the shortest integrated circuit components in embodiments where the stiffener component will be used to provide a thermal conduction path to a subsequently-formed heat sink lid/cover. As indicated by the dashed lines, the stiffener attachment step 83 is an optional step that may be omitted from the fabrication sequence. Alternatively, the stiffener attachment step 83 may occur simultaneously with or even before the dice attachment step 82.
At step 84, an optional warpage mitigation step may be performed to mitigate any warpage on the package substrate. In selected embodiments, the warpage mitigation step may include applying a magnetic field which interacts with a magnetic stiffener ring or structure to clamp or straighten out warpage in the carrier. In addition or in the alternative, the warpage mitigation step may include forming localized solder extension layers on the substrate landing pads of the substrate to close any gap between the integrated circuit components and package substrate. As indicated by the dashed lines, the warpage mitigation step 84 is an optional step that may be omitted from the fabrication sequence.
At step 85, the multi-height integrated circuit components (and any stiffener elements) are encapsulated and covered with a molding compound. By covering or encapsulating integrated circuit components with a suitable encapsulant material, such as an epoxy molding compound which is cured to form a mold compound body that covers the circuit components, an encapsulated integrated circuit component panel is formed wherein each of the multi-height integrated circuit components extend upward by a different height from the carrier.
At step 86, a grinding or etching or laser ablation process is applied to the molding compound to form an integrated circuit component panel with leveled and exposed IC components on the backside of the integrated circuit component panel s at a flat heat dissipation surface, thereby forming a thinned encapsulated integrated circuit component panel. For example, by back-grinding the top of the molding compound to thin the encapsulated integrated circuit component panel to a desired thickness that is at least as tall as the shortest integrated circuit component, the multi-height integrated circuit components (and any stiffener elements) are etched or grinded to a uniform height and are exposed at the top of the etched molding compound.
At step 87, interconnect conductor elements (e.g., microbump) may optionally be formed on the contact terminal(s) (e.g., landing pads) of the leveled integrated circuit components. In order to form the interconnect conductor elements, the thinned encapsulated integrated circuit component panel is removed from the carrier, cleaned, flipped, and mounted to a second carrier, such as a process carrier or other suitable substrate, using any desired attachment or adhesive mechanism. In selected embodiments, the interconnect conductor elements may be built on the active surfaces of the thinned encapsulated integrated circuit component panel to make electrical contact with exposed contact terminals of the integrated circuit components, such as by sequentially depositing, patterning, etching insulating layers and conductive layers (e.g., plated copper) to form fine pitched plated conductor lines. As indicated by the dashed lines, the interconnect formation step 87 is an optional step that may be omitted from the fabrication sequence when the multi-height integrated circuit components already include first level interconnect conductors (e.g., microbumps).
At step 88, the thinned encapsulated integrated circuit component panel may be singulated into individual IC component panel modules which are assembled or attached to one or more multi-chip package substrates which each include embedded active and/or passive elements which are sandwiched between a fine pitch RDL stack and coarse pitch RDL stack. In selected embodiments, the thinned encapsulated integrated circuit component panel is singulated using a saw, laser, or other cutting process which separates the thinned encapsulated integrated circuit component panel into a plurality of individual IC component panel modules, each having a plurality of IC components exposed in the molding compound by a flat heat dissipation surface. In selected embodiments, the singulation process forms IC component panel modules which are then attached to corresponding multi-chip package substrates. In other embodiments, the singulation process forms an IC component panel modules attached to corresponding multi-chip package substrates.
At step 89, a heat sink or spreader lid/cover is assembled or formed in thermal contact with the exposed backsides of the thinned integrated circuit components, thereby forming a package assembly which includes the multi-chip package substrate, individual IC component panels or modules, and attached heat sink or spreader lid/cover. In selected embodiments, the formation or assembly of the heat sink or spreader lid/cover includes placing the heat sink or spreader lid/cover in registry with and attached to directly thermally contact the plurality of IC components at the flat heat dissipation surface, either directly or through one or more thermally conductive TIM and/or BSM layers. In addition, the heat sink or spreader lid/cover may be attached with thermally conductive stiffener structures to enable thermal dissipation from embedded active/passive elements in the multi-chip package substrate(s). At this point, the package assembly may be placed in a tray and sent for inspection, testing, and laser marking. The process ends at step 90.
By now it should be appreciated that there is provided herein a method and apparatus for making a package assembly. In the disclosed methodology, a first plurality of surface-attachable devices is attached to a temporary carrier, where the first plurality of surface-attachable devices have different heights and interconnect surfaces facing the temporary carrier. In selected embodiments, the plurality of surface-attachable devices includes devices from a group consisting of integrated circuit devices, active devices, passive devices, and/or photonics components. In selected embodiments, the surface-attachable devices are attached to the temporary carrier by attaching a plurality of integrated circuit dice have different heights to the temporary carrier, where each integrated circuit die includes an interconnect surface with landing pad connections. In other embodiments, each integrated circuit die includes an assembly interface of microbump conductors connected, respectively, to the landing pad connections. The disclosed methodology also includes encapsulating the first plurality of surface-attachable devices with a molding compound material that completely covers the first plurality of surface-attachable devices. In addition, the disclosed methodology may include curing the molding compound material to form a first panel of surface-attachable devices having different heights. The disclosed methodology also includes grinding or etching a backside surface of the first panel of surface-attachable devices to thin at least one of the first plurality of surface-attachable devices, thereby forming a thinned panel of surface-attachable devices which have a uniform height. In addition, the disclosed methodology includes singulating the thinned panel of surface-attachable devices into a plurality of integrated circuit packages so that each integrated circuit package includes an encapsulated plurality of surface-attachable devices which have the uniform height, has a planar frontside surface exposing circuit connections on interconnect surfaces of the encapsulated plurality of surface-attachable devices, and has a planar heat dissipation surface exposing backsides of the encapsulated plurality of surface-attachable devices. The disclosed methodology also includes attaching the planar frontside surface of each integrated circuit package to a multichip package substrate to make electric connection between (1) the circuit connections on the interconnect surfaces of the encapsulated plurality of surface-attachable devices and (2) conducting elements in a first redistribution line stack formed on the multichip package substrate which includes a plurality of embedded active and/or passive circuit components sandwiched between the first redistribution line stack and a second redistribution line stack. In addition, the disclosed methodology attaches a heat spreader lid to the planar heat dissipation surface of each integrated circuit package so that the heat spreader lid is thermally connected to dissipate heat from the encapsulated plurality of surface-attachable devices through the planar heat dissipation surface. In selected embodiments, the heat spreader lid is attached to make a thermal conduction path to the embedded active and/or passive circuit components in the multichip package substrate over thermal conducting elements in the first redistribution line stack formed on the multichip package substrate. In selected embodiments, the disclosed methodology may also include forming one or more thermally conductive interface layers on the planar heat dissipation surface of each integrated circuit package before attaching the heat spreader lid to the planar heat dissipation surface of each integrated circuit package. In such embodiments, the thermally conductive interface layer(s) may be formed by first forming a first backside metallization layer on the planar heat dissipation surface of each integrated circuit package, and then forming a thermal interface layer on the backside metallization layer of each integrated circuit package. In selected embodiments, the disclosed methodology may also include forming one or more thermally conductive adhesive layers on the multichip package substrate or heat spreader lid to attach the heat spreader lid to the multichip package substrate and to provide a heat dissipation path to the embedded active and/or passive circuit components in the multichip package substrate over thermal conducting elements in the first redistribution line stack formed on the multichip package substrate.
In another form, there is provided a method and apparatus for making a package assembly. In the disclosed methodology, a first plurality of multichip package substrates is attached to a carrier, where each multichip package substrate includes a plurality of embedded active and/or passive circuit components sandwiched between a first redistribution line stack and a second redistribution line stack. The disclosed methodology also includes attaching, to each multichip package substrate, a first plurality of surface-attachable devices which have different heights and interconnect surfaces facing a corresponding multichip package substrate. In selected embodiments, the plurality of surface-attachable devices includes devices from a group consisting of integrated circuit devices, active devices, passive devices, and/or photonics components. In addition, the disclosed methodology includes encapsulating the first plurality of surface-attachable devices at each multichip package substrate with a molding compound material that completely covers the first plurality of surface-attachable devices without covering the interconnect surfaces, and then curing the molding compound material to form a first panel of surface-attachable devices having different heights which is attached to the first plurality of multichip package substrates. The disclosed methodology also includes grinding or etching a backside surface of the first panel of surface-attachable devices to thin at least one of the first plurality of surface-attachable devices, thereby forming a thinned panel of surface-attachable devices having a uniform height which is attached to the first plurality of multichip package substrates. In addition, the disclosed methodology includes singulating the thinned panel of surface-attachable devices and attached first plurality of multichip package substrates into a plurality of integrated circuit packages, where each integrated circuit package includes an encapsulated plurality of surface-attachable devices having the uniform height which are attached to a corresponding multichip package substrate, and where each integrated circuit package has a planar heat dissipation surface exposing backsides of the encapsulated plurality of surface-attachable devices. The disclosed methodology also includes attaching a heat spreader lid to the planar heat dissipation surface of each integrated circuit package so that the heat spreader lid is thermally connected to dissipate heat from the encapsulated plurality of surface-attachable devices through the planar heat dissipation surface. In selected embodiments, the disclosed methodology also includes forming one or more thermally conductive interface layers on the planar heat dissipation surface of each integrated circuit package before attaching the heat spreader lid to the planar heat dissipation surface of each integrated circuit package. In selected embodiments, the disclosed methodology also includes attaching, to each multichip package substrate, a stiffener ring surrounding first plurality of surface-attachable devices which is subsequently encapsulated by the molding compound material to be included in each integrated circuit package. In such embodiments, the heat spreader lid is attached to make a thermal conduction path through the stiffener ring to the embedded active and/or passive circuit components in the multichip package substrate over thermal conducting elements in the first redistribution line stack formed on the multichip package substrate. In addition, one or more thermally conductive adhesive layers may be formed on the multichip package substrate or the stiffener ring to attach the heat spreader lid to the multichip package substrate and to provide a heat dissipation path to the embedded active and/or passive circuit components in the multichip package substrate over thermal conducting elements in the first redistribution line stack formed on the multichip package substrate. In selected embodiments, the stiffener ring is formed with a magnetic material which will respond to a magnetic field to exert a physical clamping force on the multichip package substrate. In other embodiments, the first plurality of surface-attachable devices are attached to each multichip package substrate by applying localized landing pad conductive material extension layers (such as solder, conductive paste, metal, metal alloy, thermal paste, thermal pad, etc.) to selected conductive landing pads in the first redistribution line stack where warpage of the multichip package substrate has created a gap between the selected conductive landing and circuit connections on the interconnect surfaces of the encapsulated plurality of surface-attachable devices. In selected embodiments, the localized landing pad conductive material extension layers are formed with one or more layers of solder, copper paste, silver paste, and/or copper, and are formed to a thickness to compensate for the warpage where an interconnect surface area is further away from the multichip package substrate. In selected embodiments, the localized landing pad conductive material extension layers are localized to compensate for the warpage where the active surface area is further away from the substrate. Further, the height of the added localized landing pad conductive material extension layers can also vary according to the warpage.
In yet another form, there is provided an integrated circuit package assembly and method for making same. As disclosed, the integrated circuit package assembly includes an encapsulated plurality of integrated circuit dice which is attached to a multichip package substrate having embedded active and/or passive circuit devices. The encapsulated plurality of integrated circuit dice is also attached to a heat spreader lid that is formed on and thermally connected to the encapsulated plurality of integrated circuit dice. As formed, the heat spreader lid includes one or more thermal conductive layers to remove heat from the encapsulated plurality of integrated circuit dice. In addition, the encapsulated plurality of integrated circuit dice are surrounded by a molding compound on all side surfaces but not a top surface facing away from the multi-chip package substrate that provides a planar heat dissipation surface that is directly thermally connected to the heat spreader lid to dissipate heat from the encapsulated plurality of integrated circuit dice through the planar heat dissipation surface. In selected embodiments, the heat spreader lid is thermally connected to the embedded active and/or passive circuit devices with one or more thermal conductive layers to remove heat from the embedded active and/or passive circuit devices.
Various illustrative embodiments of the present invention have been described in detail with reference to the accompanying figures. While various details are set forth in the foregoing description, it will be appreciated that the present invention may be practiced without these specific details, and that numerous implementation-specific decisions may be made to the invention described herein to achieve the device designer's specific goals, such as compliance with process technology or design-related constraints, which will vary from one implementation to another. While such a development effort might be complex and time-consuming, it would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. For example, selected aspects are depicted with reference to simplified cross-sectional drawings and flow charts illustrating process and structural details of a package assembly and associated fabrication process without including every device feature or aspect in order to avoid limiting or obscuring the present invention. Such descriptions and representations are used by those skilled in the art to describe and convey the substance of their work to others skilled in the art, and the omitted details which are well known are not considered necessary to teach one skilled in the art of how to make or use the present invention. In addition, certain elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. It is also noted that, throughout this detailed description, certain layers of materials will be deposited, removed and otherwise processed to form the depicted integrated circuit die and associated packaging structures. Where the specific procedures for forming such layers are not detailed below, conventional techniques to one skilled in the art for depositing, removing or otherwise forming such layers at appropriate thicknesses shall be intended. Such details are well known and not considered necessary to teach one skilled in the art of how to make or use the present invention.
Although the described exemplary embodiments disclosed herein are directed to various packaging assemblies and methods for making same, the present invention is not necessarily limited to the example embodiments which illustrate inventive aspects of the present invention that are applicable to a wide variety of packaging processes and/or devices. Thus, the particular embodiments disclosed above are illustrative only and should not be taken as limitations upon the present invention, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the multi-chip package substrates are described with reference to embedded passive components, such as capacitors, resistors, inductors, diodes, and other passive devices, but active devices may also be included as embedded components when forming the multi-chip package substrates, so these are merely exemplary circuits presented to provide a useful reference in discussing various aspects of the invention, and is not intended to be limiting so that persons of skill in the art will understand that the principles taught herein apply to other types of devices. In addition, the process steps may be performed in an alternative order than what is presented. Also, the figures do not show all the details of connections between various elements of the package, since it will be appreciated the leads, vias, bonds, circuit traces, and other connection means can be used to effect any electrical connection. Accordingly, the foregoing description is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. In addition, the term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
