Sin S. Tan

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 11,449,446
- Issue date Sep 20, 2022
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced cyclical redundancy check circuit based on galois-field ar...
- Patent number 9,935,653
- Issue date Apr 3, 2018
- Intel Corporation
- Sivakumar Radhakrishnan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Presentation of direct accessed storage under a logical drive model
- Patent number 9,417,821
- Issue date Aug 16, 2016
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and scalable cyclic redundancy check circuit using Galois...
- Patent number 9,141,469
- Issue date Sep 22, 2015
- Intel Corporation
- Sivakumar Radhakrishnan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integration of processor and input/output hub
- Patent number 8,850,250
- Issue date Sep 30, 2014
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Limiting false wakeups of computing device components coupled via l...
- Patent number 8,812,878
- Issue date Aug 19, 2014
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic and idle power reduction sequence using recombinant clock a...
- Patent number 8,782,456
- Issue date Jul 15, 2014
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and scalable cyclic redundancy check circuit using Galois...
- Patent number 8,607,129
- Issue date Dec 10, 2013
- Intel Corporation
- Sivakumar Radhakrishnan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic squelch detection power control
- Patent number 8,352,764
- Issue date Jan 8, 2013
- Intel Corporation
- Sin Tan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Power measurement techniques of a system-on-chip (SOC)
- Patent number 8,275,560
- Issue date Sep 25, 2012
- Intel Corporation
- Sivakumar Radhakrishnan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Maximal length packets
- Patent number 7,500,029
- Issue date Mar 3, 2009
- Intel Corporation
- Sivakumar Radhakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to guarantee forward progress for incoming coherent input...
- Patent number 7,386,643
- Issue date Jun 10, 2008
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to resolve instruction starvation
- Patent number 7,065,596
- Issue date Jun 20, 2006
- Intel Corporation
- S. Steven Kulick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to guarantee forward progress for incoming coherent input...
- Patent number 6,832,268
- Issue date Dec 14, 2004
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for preventing starvation in a multi-node arch...
- Patent number 6,826,619
- Issue date Nov 30, 2004
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for handling conflicts in a multi-node computer architecture
- Patent number 6,622,215
- Issue date Sep 16, 2003
- Intel Corporation
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherent variable length reads from system memory
- Patent number 6,298,420
- Issue date Oct 2, 2001
- Intel Corporation
- Suresh Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controller that supports data merging utilizing a slice addressable...
- Patent number 6,134,632
- Issue date Oct 17, 2000
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherent variable length reads which implicates multiple cache line...
- Patent number 6,061,764
- Issue date May 9, 2000
- Intel Corporation
- Suresh Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Individually resettable bus expander bridge mechanism
- Patent number 5,996,038
- Issue date Nov 30, 1999
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20200349100
- Publication date Nov 5, 2020
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED CYCLICAL REDUNDANCY CHECK CIRCUIT BASED ON GALOIS-FIELD AR...
- Publication number 20170187389
- Publication date Jun 29, 2017
- Intel Corporation
- Sivakumar Radhakrishnan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20160335208
- Publication date Nov 17, 2016
- Intel Corporation
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL
- Publication number 20140189212
- Publication date Jul 3, 2014
- Thomas M. Slaight
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS...
- Publication number 20140082451
- Publication date Mar 20, 2014
- Sivakumar Radhakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS...
- Publication number 20130007573
- Publication date Jan 3, 2013
- Sivakumar Radhakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB
- Publication number 20110296216
- Publication date Dec 1, 2011
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK A...
- Publication number 20110296222
- Publication date Dec 1, 2011
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC)
- Publication number 20110060931
- Publication date Mar 10, 2011
- SIVAKUMAR RADHAKRISHNAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SQUELCH FILTRATION TO LIMIT FALSE WAKEUPS
- Publication number 20100332868
- Publication date Dec 30, 2010
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic squelch detection power control
- Publication number 20100081406
- Publication date Apr 1, 2010
- Sin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique and apparatus for combining partial write transactions
- Publication number 20080235461
- Publication date Sep 25, 2008
- Sin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Maximal length packets
- Publication number 20060168384
- Publication date Jul 27, 2006
- Sivakumar Radhakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to guarantee forward progress for incoming coherent input...
- Publication number 20050060502
- Publication date Mar 17, 2005
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to guarantee forward progress for incoming coherent input...
- Publication number 20040122995
- Publication date Jun 24, 2004
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to resolve instruction starvation
- Publication number 20040068597
- Publication date Apr 8, 2004
- S. Steven Kulick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for handling conflicts in a multi-node computer architecture
- Publication number 20020129206
- Publication date Sep 12, 2002
- Manoj Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to implement a locked-bus transaction
- Publication number 20020087766
- Publication date Jul 4, 2002
- Akhilesh Kumar
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Presentation of direct accessed storage under a logical drive model

Enhanced cyclical redundancy check circuit based on galois-field ar...

Presentation of direct accessed storage under a logical drive model

Efficient and scalable cyclic redundancy check circuit using Galois...

Integration of processor and input/output hub

Limiting false wakeups of computing device components coupled via l...

Dynamic and idle power reduction sequence using recombinant clock a...

Efficient and scalable cyclic redundancy check circuit using Galois...

Dynamic squelch detection power control

Power measurement techniques of a system-on-chip (SOC)

Maximal length packets

Mechanism to guarantee forward progress for incoming coherent input...

Method and apparatus to resolve instruction starvation

Mechanism to guarantee forward progress for incoming coherent input...

Method and apparatus for preventing starvation in a multi-node arch...

Mechanism for handling conflicts in a multi-node computer architecture

Coherent variable length reads from system memory

Controller that supports data merging utilizing a slice addressable...

Coherent variable length reads which implicates multiple cache line...

Individually resettable bus expander bridge mechanism

Patents Applicationslast 30 patents

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

ENHANCED CYCLICAL REDUNDANCY CHECK CIRCUIT BASED ON GALOIS-FIELD AR...

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL

EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS...

EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS...

INTEGRATION OF PROCESSOR AND INPUT/OUTPUT HUB

DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK A...

POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC)

SQUELCH FILTRATION TO LIMIT FALSE WAKEUPS

Dynamic squelch detection power control

Technique and apparatus for combining partial write transactions

Maximal length packets

Mechanism to guarantee forward progress for incoming coherent input...

Mechanism to guarantee forward progress for incoming coherent input...

Method and apparatus to resolve instruction starvation

Mechanism for handling conflicts in a multi-node computer architecture

Method and apparatus to implement a locked-bus transaction