Song Zhao

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low temperature coefficient resistor in CMOS flow
- Patent number 9,543,374
- Issue date Jan 10, 2017
- Texas Instruments Incorporated
- Greg Charles Baldwin
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
MOSFET with source side only stress
- Patent number 9,412,869
- Issue date Aug 9, 2016
- Texas Instruments Incorporated
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature coefficient resistor in CMOS flow
- Patent number 8,940,598
- Issue date Jan 27, 2015
- Texas Instruments Incorporated
- Greg Charles Baldwin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET with source side only stress
- Patent number 8,928,047
- Issue date Jan 6, 2015
- Texas Instruments Incorporated
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having silicide block resistor
- Patent number 8,748,256
- Issue date Jun 10, 2014
- Texas Instruments Incorporated
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS fabrication process
- Patent number 8,125,035
- Issue date Feb 28, 2012
- Texas Instruments Incorporated
- Mahalingam Nandakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress memorization dielectric optimized for NMOS and PMOS
- Patent number 8,101,476
- Issue date Jan 24, 2012
- Texas Instruments Incorporated
- Kanan Garg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor doping with reduced gate edge diode leakage
- Patent number 7,897,496
- Issue date Mar 1, 2011
- Texas Instruments Incorporated
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS fabrication process
- Patent number 7,678,637
- Issue date Mar 16, 2010
- Texas Instruments Incorporated
- Mahalingam Nandakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design method and system for optimum performance in integrated circ...
- Patent number 7,216,310
- Issue date May 8, 2007
- Texas Instruments Incorporated
- Amitava Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to strain NMOS devices while mitigating dopant diffusion for...
- Patent number 7,211,481
- Issue date May 1, 2007
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide method for CMOS integrated circuits
- Patent number 7,029,967
- Issue date Apr 18, 2006
- Texas Instruments Incorporated
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process to reduce gate edge drain leakage in semiconductor devices
- Patent number 6,855,984
- Issue date Feb 15, 2005
- Texas Instruments Incorporated
- Zhiqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Additional n-type LDD/pocket implant for improving short-channel NM...
- Patent number 6,822,297
- Issue date Nov 23, 2004
- Texas Instruments Incorporated
- Mahalingam Nandakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel implant for improving NMOS ESD robustness
- Patent number 6,452,236
- Issue date Sep 17, 2002
- Texas Instruments, Incorporated
- Mahalingam Nadakumar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS TO TUNE THRESHOLD VOLTAGE OF DEVICE WITH HIGH...
- Publication number 20160172443
- Publication date Jun 16, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW
- Publication number 20150171158
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Greg Charles BALDWIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOSFET WITH SOURCE SIDE ONLY STRESS
- Publication number 20150087127
- Publication date Mar 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING SILICIDE BLOCK RESISTOR
- Publication number 20130200466
- Publication date Aug 8, 2013
- TEXAS INSTRUMENTS INCORPORATED
- SONG ZHAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOSFET WITH SOURCE SIDE ONLY STRESS
- Publication number 20120146054
- Publication date Jun 14, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW
- Publication number 20120108020
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Greg Charles BALDWIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Novel Method to Improve Performance by Enhancing Poly Gate Doping C...
- Publication number 20110306170
- Publication date Dec 15, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Xin WANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS MEMORIZATION DIELECTRIC OPTIMIZED FOR NMOS AND PMOS
- Publication number 20100210081
- Publication date Aug 19, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Kanan GARG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Fabrication Process
- Publication number 20100133624
- Publication date Jun 3, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Mahalingam Nandakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE
- Publication number 20090127620
- Publication date May 21, 2009
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Fabrication Process
- Publication number 20090079008
- Publication date Mar 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Mahalingam Nandakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to strain NMOS devices while mitigating dopant diffusion for...
- Publication number 20060189048
- Publication date Aug 24, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide method for CMOS integrated circuits
- Publication number 20060019478
- Publication date Jan 26, 2006
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Design method and system for optimum performance in integrated circ...
- Publication number 20050149887
- Publication date Jul 7, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Amitava Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Additional n-type LDD/pocket implant for improving short-channel NM...
- Publication number 20020185682
- Publication date Dec 12, 2002
- Mahalingam Nandakumar
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Low temperature coefficient resistor in CMOS flow

MOSFET with source side only stress

Low temperature coefficient resistor in CMOS flow

MOSFET with source side only stress

Integrated circuit having silicide block resistor

CMOS fabrication process

Stress memorization dielectric optimized for NMOS and PMOS

Semiconductor doping with reduced gate edge diode leakage

CMOS fabrication process

Design method and system for optimum performance in integrated circ...

Method to strain NMOS devices while mitigating dopant diffusion for...

Silicide method for CMOS integrated circuits

Process to reduce gate edge drain leakage in semiconductor devices

Additional n-type LDD/pocket implant for improving short-channel NM...

Channel implant for improving NMOS ESD robustness

Patents Applicationslast 30 patents

METHOD AND APPARATUS TO TUNE THRESHOLD VOLTAGE OF DEVICE WITH HIGH...

LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW

MOSFET WITH SOURCE SIDE ONLY STRESS

INTEGRATED CIRCUIT HAVING SILICIDE BLOCK RESISTOR

MOSFET WITH SOURCE SIDE ONLY STRESS

LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW

Novel Method to Improve Performance by Enhancing Poly Gate Doping C...

STRESS MEMORIZATION DIELECTRIC OPTIMIZED FOR NMOS AND PMOS

CMOS Fabrication Process

SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE

CMOS Fabrication Process

Method to strain NMOS devices while mitigating dopant diffusion for...

Silicide method for CMOS integrated circuits

Design method and system for optimum performance in integrated circ...

Additional n-type LDD/pocket implant for improving short-channel NM...