The invention is generally related to the field of forming transistors in semiconductor devices and more specifically to improving performance in a PMOS transistor.
Historically, most performance improvements in semiconductor field-effect transistors (FET) have been achieved by scaling down the relative dimensions of the device. This trend is becoming increasingly more difficult to maintain as the devices reach their physical scaling limits. As a consequence, advanced FETs and the complementary metal oxide semiconductor (CMOS) circuits in which they can be found are increasingly relying on strain engineering and specialty silicon-on-insulator substrates to achieve desired circuit performance.
One method of introducing compressive strain in a silicon channel region is to epitaxially grow a silicon-germanium (SiGe) material within recesses formed in the semiconductor body. The silicon germanium atom has a different lattice spacing than the silicon atom thereby imparting a compressive strain to the channel region under the gate. This is referred to as an embedded SiGe process.
As with more conventional transistors, high poly gate doping concentration improves on-state current in metal oxide semiconductor transistors. It is common for integrated circuits (ICs) to pre-dope poly gate over the PMOS transistors or increase PMOS source/drain (S/D) implant dose and (or) energy to increase doping concentration in poly gate. Pre-doping poly gate requires additional mask level to block p-type implant from NMOS region. High PMOS S/D implant dose increases the S/D overrun risk, which increases leakage current, and increases the SiGe relaxation caused by S/D implant.
Improved performance in PMOS transistors fabricated using an embedded SiGe process is desired.
This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
The invention provides a novel embedded SiGe (eSiGe) PMOS process to improve PMOS poly gate doping concentration without increasing mask count and causing S/D overrun issue. After gate sidewall spacer formation, the gate electrode and source/drain regions are implanted. After the implant, a recess is formed and SiGe is deposited in the recess. By implanting and removing the implanted material from the source/drain regions prior to SiGe deposition, high PMOS gate doping can be achieved without causing a S/D overrun issue.
An advantage of the invention is providing an embedded SiGe process with improved PMOS transistor performance.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
In the drawings:
The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
The invention will now be described in conjunction with an embedded SiGe PMOS transistor and its fabrication.
Gate electrode 108 comprises highly doped p-type polysilicon. High polysilicon gate doping concentration improves on-state current. The doping concentration of gate electrode 108 may be in the range of 1020/cm3 to 10e21/cm3. Advantageously, gate electrode 108 is highly doped without excessively doping the SiGe source/drain regions 106, thus avoiding a dopant overrun issue (e.g., increased leakage current, and/or increased SiGe relaxation caused by S/D implant).
A process for forming the embedded SiGe PMOS transistor of
Still referring to
Instead of forming recesses in substrate 100 for the SiGe source/drain regions immediately after forming sidewall spacers 112, the inventive process flow performs a source/drain implant with high dose and energy. Referring to
Next, a masked silicon recess etch is performed to remove portions of the substrate where PMOS source/drain regions are desired. As a result, the implanted regions 122 are removed as shown in
In a first embodiment of the invention, recesses 124 are then filled with SiGe to form embedded SiGe source/drain (S/D) regions 106 as shown in
After the SiGe deposition, an anneal may be performed to activate the implanted dopants in the Si. The anneal is typically done with 1000 C to 1050 RTA for a few seconds or laser anneal at 1200 C-1300 C for a few milli-seconds.
Alternatively, the anneal may be performed prior to epitaxially depositing SiGe to form source/drain regions 106. An advantage of performing the anneal first is reduce the chances of SiGe relaxation during anneal. Conversely, an advantage of performing the anneal last is to reduce the diffusion of PMOS S/D implanted dopants. This help to ensure the PMOS S/D dopants are etched away during the recess etch.
Processing may continue as is known in the art with the removal of hard mask 114, formation of silicide regions at the surface of the gate electrode 108 and source/drain regions 106, the formation of contacts and interconnect layers as well as packaging of the device.
It should be noted that while the above process described the formation of a PMOS transistor, NMOS transistors and other devices may be formed concurrently with PMOS transistor 102.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
This application claims the priority of U.S. Provisional Application Ser. No. 61/093,031, filed Aug. 29, 2008, entitled “Novel Method to Improve Performance by Enhance Poly Gate Doping Concentration in an Embedded SiGe PMOS Process”. This application is related to co-pending U.S. application Ser. No. ______ (TI-66902), filed ______, and entitled “DISPOSABLE SPACER INTEGRATION WITH STRESS MEMORIZATION TECHNIQUE AND SILICON-GERMANIUM”.
Number | Date | Country | |
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61093031 | Aug 2008 | US |