Sourav Saha

Person

Barrackpur, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,956,644
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,534,884
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,417,366
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,366,191
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,242,140
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,235,487
- Issue date Mar 19, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Congestion aware layer promotion
- Patent number 10,229,238
- Issue date Mar 12, 2019
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement clustering-based white space reservation
- Patent number 10,223,489
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,223,491
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing constraints formulation for highly replicated design modules
- Patent number 10,169,523
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Chithra Ravindranath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 10,169,519
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical region identification
- Patent number 10,140,414
- Issue date Nov 27, 2018
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global routing framework of integrated circuit based on localized r...
- Patent number 10,120,970
- Issue date Nov 6, 2018
- International Business Machines Corporation
- Dirk Mueller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 9,946,830
- Issue date Apr 17, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 9,928,329
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 9,910,948
- Issue date Mar 6, 2018
- International Buisiness Machines Corporatoin
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraint-driven pin optimization for hierarchical design convergence
- Patent number 9,858,377
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-hierarchy interconnect adjustment for power recovery
- Patent number 9,798,847
- Issue date Oct 24, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Slack redistribution for additional power recovery
- Patent number 9,734,268
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control path power adjustment for chip design
- Patent number 9,734,270
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical wire-pin co-optimization
- Patent number 9,715,572
- Issue date Jul 25, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical aware technology mapping in synthesis
- Patent number 9,715,565
- Issue date Jul 25, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physical aware technology mapping in synthesis
- Patent number 9,710,585
- Issue date Jul 18, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intra-run design decision process for circuit synthesis
- Patent number 9,703,920
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing constraints formulation for highly replicated design modules
- Patent number 9,703,923
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Chithra Ravindranath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing constraints formulation for highly replicated design modules
- Patent number 9,703,924
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Chithra Ravindranath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control path power adjustment for chip design
- Patent number 9,703,910
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical wire-pin co-optimization
- Patent number 9,697,322
- Issue date Jul 4, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intra-run design decision process for circuit synthesis
- Patent number 9,690,900
- Issue date Jun 27, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-hierarchy interconnect adjustment for power recovery
- Patent number 9,684,757
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190294739
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20190220570
- Publication date Jul 18, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065635
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065636
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20180189439
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION
- Publication number 20180150584
- Publication date May 31, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101625
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101626
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL ROUTING FRAMEWORK OF INTEGRATED CIRCUIT BASED ON LOCALIZED R...
- Publication number 20170357744
- Publication date Dec 14, 2017
- International Business Machines Corporation
- Dirk Mueller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20170351798
- Publication date Dec 7, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212969
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212970
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20170154148
- Publication date Jun 1, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRAINT-DRIVEN PIN OPTIMIZATION FOR HIERARCHICAL DESIGN CONVERGENCE
- Publication number 20170132349
- Publication date May 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-HIERARCHY INTERCONNECT ADJUSTMENT FOR POWER RECOVERY
- Publication number 20170091370
- Publication date Mar 30, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES
- Publication number 20170091374
- Publication date Mar 30, 2017
- International Business Machines Corporation
- Chithra Ravindranath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC STRUCTURE AWARE CIRCUIT ROUTING
- Publication number 20170083656
- Publication date Mar 23, 2017
- International Business Machines Corporation
- Saurabh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC STRUCTURE AWARE CIRCUIT ROUTING
- Publication number 20170083657
- Publication date Mar 23, 2017
- International Business Machines Corporation
- Saurabh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES
- Publication number 20170083662
- Publication date Mar 23, 2017
- International Business Machines Corporation
- Chithra Ravindranath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES
- Publication number 20170061060
- Publication date Mar 2, 2017
- International Business Machines Corporation
- Chithra Ravindranath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES
- Publication number 20170061065
- Publication date Mar 2, 2017
- International Business Machines Corporation
- Chithra Ravindranath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLACK REDISTRIBUTION FOR ADDITIONAL POWER RECOVERY
- Publication number 20170046463
- Publication date Feb 16, 2017
- International Busines Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLACK REDISTRIBUTION FOR ADDITIONAL POWER RECOVERY
- Publication number 20170046464
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC STRUCTURE AWARE CIRCUIT ROUTING
- Publication number 20170046467
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Saurabh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONGESTION AWARE LAYER PROMOTION
- Publication number 20170046468
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC STRUCTURE AWARE CIRCUIT ROUTING
- Publication number 20170046466
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Saurabh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL PATH POWER ADJUSTMENT FOR CHIP DESIGN
- Publication number 20170011156
- Publication date Jan 12, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-HIERARCHY INTERCONNECT ADJUSTMENT FOR POWER RECOVERY
- Publication number 20170011158
- Publication date Jan 12, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-HIERARCHY INTERCONNECT ADJUSTMENT FOR POWER RECOVERY
- Publication number 20170011159
- Publication date Jan 12, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL WIRE-PIN CO-OPTIMIZATION
- Publication number 20170011163
- Publication date Jan 12, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING

Sourav Saha

Person

Patents Grantslast 30 patents

Integrated circuit design changes using through-silicon vias

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Congestion aware layer promotion

Placement clustering-based white space reservation

Integrated circuit design changes using through-silicon vias

Timing constraints formulation for highly replicated design modules

Area sharing between multiple large block synthesis (LBS) blocks

Critical region identification

Global routing framework of integrated circuit based on localized r...

Area sharing between multiple large block synthesis (LBS) blocks

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Constraint-driven pin optimization for hierarchical design convergence

Cross-hierarchy interconnect adjustment for power recovery

Slack redistribution for additional power recovery

Control path power adjustment for chip design

Hierarchical wire-pin co-optimization

Physical aware technology mapping in synthesis

Physical aware technology mapping in synthesis

Intra-run design decision process for circuit synthesis

Timing constraints formulation for highly replicated design modules

Timing constraints formulation for highly replicated design modules

Control path power adjustment for chip design

Hierarchical wire-pin co-optimization

Intra-run design decision process for circuit synthesis

Cross-hierarchy interconnect adjustment for power recovery

Patents Applicationslast 30 patents

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

GLOBAL ROUTING FRAMEWORK OF INTEGRATED CIRCUIT BASED ON LOCALIZED R...

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

CONSTRAINT-DRIVEN PIN OPTIMIZATION FOR HIERARCHICAL DESIGN CONVERGENCE

CROSS-HIERARCHY INTERCONNECT ADJUSTMENT FOR POWER RECOVERY

TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES

LOGIC STRUCTURE AWARE CIRCUIT ROUTING

LOGIC STRUCTURE AWARE CIRCUIT ROUTING

TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES

TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES

TIMING CONSTRAINTS FORMULATION FOR HIGHLY REPLICATED DESIGN MODULES

SLACK REDISTRIBUTION FOR ADDITIONAL POWER RECOVERY

SLACK REDISTRIBUTION FOR ADDITIONAL POWER RECOVERY

LOGIC STRUCTURE AWARE CIRCUIT ROUTING

CONGESTION AWARE LAYER PROMOTION

LOGIC STRUCTURE AWARE CIRCUIT ROUTING

CONTROL PATH POWER ADJUSTMENT FOR CHIP DESIGN

CROSS-HIERARCHY INTERCONNECT ADJUSTMENT FOR POWER RECOVERY

CROSS-HIERARCHY INTERCONNECT ADJUSTMENT FOR POWER RECOVERY

HIERARCHICAL WIRE-PIN CO-OPTIMIZATION