Sridhar Balakrishnan

Person

Rio Rancho, NM, US

People

Patents Grantslast 30 patents

Information Patent Grant
Designs and methods for conductive bumps
- Patent number 11,201,129
- Issue date Dec 14, 2021
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Designs and methods for conductive bumps
- Patent number 10,249,588
- Issue date Apr 2, 2019
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Designs and methods for conductive bumps
- Patent number 9,543,261
- Issue date Jan 10, 2017
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Debond interconnect structures
- Patent number 9,461,010
- Issue date Oct 4, 2016
- Intel Corporation
- Qing Ma
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Debond interconnect structures
- Patent number 9,269,686
- Issue date Feb 23, 2016
- Intel Corporation
- Qing Ma
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Debond interconnect structures
- Patent number 8,637,778
- Issue date Jan 28, 2014
- Intel Corporation
- Qing Ma
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Designs and methods for conductive bumps
- Patent number 8,580,679
- Issue date Nov 12, 2013
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier layers
- Patent number 8,508,018
- Issue date Aug 13, 2013
- Intel Corporation
- Rohan N. Akolkar
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Self-forming, self-aligned barriers for back-end interconnects and...
- Patent number 8,461,683
- Issue date Jun 11, 2013
- Intel Corporation
- Hui Jae Yoo
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Air-gap ILD with unlanded vias
- Patent number 7,772,706
- Issue date Aug 10, 2010
- Intel Corporation
- Sridhar Balakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conformal electroless deposition of barrier layer materials
- Patent number 7,629,252
- Issue date Dec 8, 2009
- Intel Corporation
- Kevin P. O'Brien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post polish anneal of atomic layer deposition barrier layers
- Patent number 7,335,587
- Issue date Feb 26, 2008
- Intel Corporation
- Steven W. Johnston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Designs and methods for conductive bumps
- Patent number 7,276,801
- Issue date Oct 2, 2007
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and an apparatus for forming an under bump metallization str...
- Patent number 6,461,954
- Issue date Oct 8, 2002
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and an apparatus for forming an under bump metallization str...
- Patent number 6,312,830
- Issue date Nov 6, 2001
- Intel Corporation
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of sealing a semiconductor substrate
- Patent number 6,054,376
- Issue date Apr 25, 2000
- Intel Corporation
- Sridhar Balakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etchback process for tungsten utilizing a NF3/AR chemistry
- Patent number 5,164,330
- Issue date Nov 17, 1992
- Intel Corporation
- Rickie L. Davis
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...
- Publication number 20240203786
- Publication date Jun 20, 2024
- Tahoe Research, Ltd.
- Hui Jae YOO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DESIGNS AND METHODS FOR CONDUCTIVE BUMPS
- Publication number 20220059484
- Publication date Feb 24, 2022
- Intel Corporation
- Valery M. DUBIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DESIGNS AND METHODS FOR CONDUCTIVE BUMPS
- Publication number 20190198472
- Publication date Jun 27, 2019
- Intel Corporation
- Valery M. DUBIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DESIGNS AND METHODS FOR CONDUCTIVE BUMPS
- Publication number 20170084564
- Publication date Mar 23, 2017
- Intel Corporation
- Valery M. DUBIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...
- Publication number 20160307796
- Publication date Oct 20, 2016
- Intel Corporation
- Hui Jae Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEBOND INTERCONNECT STRUCTURES
- Publication number 20160133596
- Publication date May 12, 2016
- Intel Corporation
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEBOND INTERCONNECT STRUCTURES
- Publication number 20140106560
- Publication date Apr 17, 2014
- Qing Ma
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...
- Publication number 20130260553
- Publication date Oct 3, 2013
- Hui Jae Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...
- Publication number 20120248608
- Publication date Oct 4, 2012
- Hui Jae Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER LAYERS
- Publication number 20120077053
- Publication date Mar 29, 2012
- Rohan N. Akolkar
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
DEBOND INTERCONNECT STRUCTURES
- Publication number 20110247872
- Publication date Oct 13, 2011
- Qing Ma
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
DESIGNS AND METHODS FOR CONDUCTIVE BUMPS
- Publication number 20110084387
- Publication date Apr 14, 2011
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dopant Enhanced Interconnect
- Publication number 20100200991
- Publication date Aug 12, 2010
- Rohan Akolkar
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Methods of forming improved electromigration resistant copper films...
- Publication number 20090321935
- Publication date Dec 31, 2009
- Kevin O'Brien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AIR-GAP ILD WITH UNLANDED VIAS
- Publication number 20090166881
- Publication date Jul 2, 2009
- Sridhar Balakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COPPER METALLIZATION UTILIZING REFLOW ON NOBLE METAL LINERS
- Publication number 20090169760
- Publication date Jul 2, 2009
- Rohan Akolkar
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Designs and methods for conductive bumps
- Publication number 20080213996
- Publication date Sep 4, 2008
- Intel Corporation
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conformal electroless deposition of barrier layer materials
- Publication number 20070148952
- Publication date Jun 28, 2007
- Kevin P. O'Brien
- B82 - NANO-TECHNOLOGY
Information Patent Application
Post polish anneal of atomic layer deposition barrier layers
- Publication number 20070004230
- Publication date Jan 4, 2007
- Steven W. Johnston
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Designs and methods for conductive bumps
- Publication number 20050062169
- Publication date Mar 24, 2005
- Valery M. Dubin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and an apparatus for forming an under bump metallization str...
- Publication number 20020028338
- Publication date Mar 7, 2002
- Jian Li
- H01 - BASIC ELECTRIC ELEMENTS

Sridhar Balakrishnan

Person

Patents Grantslast 30 patents

Designs and methods for conductive bumps

Designs and methods for conductive bumps

Designs and methods for conductive bumps

Debond interconnect structures

Debond interconnect structures

Debond interconnect structures

Designs and methods for conductive bumps

Barrier layers

Self-forming, self-aligned barriers for back-end interconnects and...

Air-gap ILD with unlanded vias

Conformal electroless deposition of barrier layer materials

Post polish anneal of atomic layer deposition barrier layers

Designs and methods for conductive bumps

Method and an apparatus for forming an under bump metallization str...

Method and an apparatus for forming an under bump metallization str...

Method of sealing a semiconductor substrate

Etchback process for tungsten utilizing a NF3/AR chemistry

Patents Applicationslast 30 patents

SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...

DEBOND INTERCONNECT STRUCTURES

DEBOND INTERCONNECT STRUCTURES

SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...

SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND...

BARRIER LAYERS

DEBOND INTERCONNECT STRUCTURES

DESIGNS AND METHODS FOR CONDUCTIVE BUMPS

Dopant Enhanced Interconnect

Methods of forming improved electromigration resistant copper films...

AIR-GAP ILD WITH UNLANDED VIAS

COPPER METALLIZATION UTILIZING REFLOW ON NOBLE METAL LINERS

Designs and methods for conductive bumps

Conformal electroless deposition of barrier layer materials

Post polish anneal of atomic layer deposition barrier layers

Designs and methods for conductive bumps

Method and an apparatus for forming an under bump metallization str...