Sridhar H. Rangarajan

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,956,644
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing error correcting code in three-dimensional stacked memory
- Patent number 10,740,177
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Saravanan Sethuraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management for memory subsystems
- Patent number 10,725,678
- Issue date Jul 28, 2020
- International Business Machines Corporation
- Arindam Raychaudhuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional stacked memory optimizations for latency and power
- Patent number 10,534,545
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional stacked memory access optimization
- Patent number 10,528,288
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit logic extraction using cloning and expansion for...
- Patent number 10,318,689
- Issue date Jun 11, 2019
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,223,491
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjusting scan connections based on scan control locations
- Patent number 10,216,885
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain latency reduction
- Patent number 10,168,386
- Issue date Jan 1, 2019
- International Business Machines Corporation
- George Antony
- G01 - MEASURING TESTING
Information Patent Grant
Critical region identification
- Patent number 10,140,414
- Issue date Nov 27, 2018
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjusting scan connections based on scan control locations
- Patent number 9,934,348
- Issue date Apr 3, 2018
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical region identification
- Patent number 9,659,140
- Issue date May 23, 2017
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-silicon via access device for integrated circuits
- Patent number 9,633,928
- Issue date Apr 25, 2017
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 9,569,580
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physically aware insertion of diagnostic circuit elements
- Patent number 9,557,381
- Issue date Jan 31, 2017
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 9,501,603
- Issue date Nov 22, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-silicon via access device for integrated circuits
- Patent number 9,412,682
- Issue date Aug 9, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Critical region identification
- Patent number 9,378,326
- Issue date Jun 28, 2016
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing operating range of an electronic circuit
- Patent number 9,087,168
- Issue date Jul 21, 2015
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational thermal analysis during microchip design
- Patent number 8,826,208
- Issue date Sep 2, 2014
- International Business Machines Corporation
- Sourav Saha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable gate array as drivers for data ports of spare latches
- Patent number 8,638,120
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Ashish Jaitly
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spare latch distribution
- Patent number 8,572,536
- Issue date Oct 29, 2013
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Native threshold voltage switching
- Patent number 8,495,553
- Issue date Jul 23, 2013
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
POWER MANAGEMENT FOR MEMORY SUBSYSTEMS
- Publication number 20190317679
- Publication date Oct 17, 2019
- International Business Machines Corporation
- Arindam Raychaudhuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20190220570
- Publication date Jul 18, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING ERROR CORRECTING CODE IN THREE-DIMENSIONAL STACKED MEMORY
- Publication number 20190220351
- Publication date Jul 18, 2019
- International Business Machines Corporation
- SARAVANAN SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL STACKED MEMORY OPTIMIZATIONS FOR LATENCY AND POWER
- Publication number 20190187915
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION
- Publication number 20190187930
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT LOGIC EXTRACTION USING CLONING AND EXPANSION FOR...
- Publication number 20180300441
- Publication date Oct 18, 2018
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN CHAIN LATENCY REDUCTION
- Publication number 20180203064
- Publication date Jul 19, 2018
- International Business Machines Corporation
- George Antony
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN LATENCY REDUCTION
- Publication number 20180203066
- Publication date Jul 19, 2018
- International Business Machines Corporation
- George Antony
- G01 - MEASURING TESTING
Information Patent Application
ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS
- Publication number 20180096091
- Publication date Apr 5, 2018
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Application
ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS
- Publication number 20170177777
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Raghu G. GopalaKrishnaSetty
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20170154148
- Publication date Jun 1, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL REGION IDENTIFICATION
- Publication number 20160217248
- Publication date Jul 28, 2016
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGION-BASED SYNTHESIS OF LOGIC CIRCUITS
- Publication number 20160117422
- Publication date Apr 28, 2016
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGION-BASED SYNTHESIS OF LOGIC CIRCUITS
- Publication number 20160117421
- Publication date Apr 28, 2016
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20160070842
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL REGION IDENTIFICATION
- Publication number 20160070845
- Publication date Mar 10, 2016
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL REGION IDENTIFICATION
- Publication number 20160070849
- Publication date Mar 10, 2016
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS
- Publication number 20160071786
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20160070840
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS
- Publication number 20160071783
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NATIVE THRESHOLD VOLTAGE SWITCHING
- Publication number 20130152028
- Publication date Jun 13, 2013
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARE LATCH DISTRIBUTION
- Publication number 20130080989
- Publication date Mar 28, 2013
- International Business Machines Corporation
- George Antony
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES
- Publication number 20130076391
- Publication date Mar 28, 2013
- International Business Machines Corporation
- Ashish Jaitly
- G06 - COMPUTING CALCULATING COUNTING

Sridhar H. Rangarajan

Person

Patents Grantslast 30 patents

Integrated circuit design changes using through-silicon vias

Optimizing error correcting code in three-dimensional stacked memory

Power management for memory subsystems

Three-dimensional stacked memory optimizations for latency and power

Three-dimensional stacked memory access optimization

Integrated circuit logic extraction using cloning and expansion for...

Integrated circuit design changes using through-silicon vias

Adjusting scan connections based on scan control locations

Scan chain latency reduction

Critical region identification

Adjusting scan connections based on scan control locations

Critical region identification

Through-silicon via access device for integrated circuits

Integrated circuit design changes using through-silicon vias

Physically aware insertion of diagnostic circuit elements

Integrated circuit design changes using through-silicon vias

Through-silicon via access device for integrated circuits

Critical region identification

Optimizing operating range of an electronic circuit

Computational thermal analysis during microchip design

Programmable gate array as drivers for data ports of spare latches

Spare latch distribution

Native threshold voltage switching

Patents Applicationslast 30 patents

POWER MANAGEMENT FOR MEMORY SUBSYSTEMS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

OPTIMIZING ERROR CORRECTING CODE IN THREE-DIMENSIONAL STACKED MEMORY

THREE-DIMENSIONAL STACKED MEMORY OPTIMIZATIONS FOR LATENCY AND POWER

THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION

INTEGRATED CIRCUIT LOGIC EXTRACTION USING CLONING AND EXPANSION FOR...

SCAN CHAIN LATENCY REDUCTION

SCAN CHAIN LATENCY REDUCTION

ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS

ADJUSTING SCAN CONNECTIONS BASED ON SCAN CONTROL LOCATIONS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

CRITICAL REGION IDENTIFICATION

REGION-BASED SYNTHESIS OF LOGIC CIRCUITS

REGION-BASED SYNTHESIS OF LOGIC CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

CRITICAL REGION IDENTIFICATION

CRITICAL REGION IDENTIFICATION

THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS

NATIVE THRESHOLD VOLTAGE SWITCHING

SPARE LATCH DISTRIBUTION

PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES