Sridhar S. Govindaraju

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques and configurations to reduce transistor gate short defects
- Patent number 12,094,780
- Issue date Sep 17, 2024
- Intel Corporation
- Sridhar Govindaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-planar semiconductor device having conforming ohmic contacts
- Patent number 11,978,776
- Issue date May 7, 2024
- Intel Corporation
- Ashutosh Sagar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations to reduce transistor gate short defects
- Patent number 11,756,833
- Issue date Sep 12, 2023
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architecture having local interconn...
- Patent number 11,705,453
- Issue date Jul 18, 2023
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual self-aligned gate endcap (SAGE) architectures
- Patent number 11,688,792
- Issue date Jun 27, 2023
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Unidirectional self-aligned gate endcap (SAGE) architectures with g...
- Patent number 11,605,632
- Issue date Mar 14, 2023
- Intel Corporation
- Walid M. Hafez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations to reduce transistor gate short defects
- Patent number 11,380,592
- Issue date Jul 5, 2022
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architecture having endcap plugs
- Patent number 11,329,138
- Issue date May 10, 2022
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Unidirectional self-aligned gate endcap (SAGE) architectures with g...
- Patent number 11,217,582
- Issue date Jan 4, 2022
- Intel Corporation
- Walid M. Hafez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual self-aligned gate endcap (SAGE) architectures
- Patent number 11,205,708
- Issue date Dec 21, 2021
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations to reduce transistor gate short defects
- Patent number 10,847,423
- Issue date Nov 24, 2020
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations to reduce transistor gate short defects
- Patent number 10,468,305
- Issue date Nov 5, 2019
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations to reduce transistor gate short defects
- Patent number 9,761,497
- Issue date Sep 12, 2017
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using materials with different etch rates to fill trenches in semic...
- Patent number 9,704,798
- Issue date Jul 11, 2017
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations to reduce transistor gate short defects
- Patent number 9,281,401
- Issue date Mar 8, 2016
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-second annealing processes for semiconductor devices
- Patent number 7,892,971
- Issue date Feb 22, 2011
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce junction leakage through partial regrowth with ult...
- Patent number 7,790,587
- Issue date Sep 7, 2010
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Temperature measurement with reduced extraneous infrared in a proce...
- Patent number 7,758,238
- Issue date Jul 20, 2010
- Intel Corporation
- Sridhar Govindaraju
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
- Publication number 20230360973
- Publication date Nov 9, 2023
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
- Publication number 20220262684
- Publication date Aug 18, 2022
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES
- Publication number 20220077302
- Publication date Mar 10, 2022
- Intel Corporation
- Sairam SUBRAMANIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH G...
- Publication number 20220077145
- Publication date Mar 10, 2022
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
- Publication number 20210028066
- Publication date Jan 28, 2021
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING LOCAL INTERCONN...
- Publication number 20200286891
- Publication date Sep 10, 2020
- Intel Corporation
- Sairam SUBRAMANIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING CONFORMING OHMIC CONTACTS
- Publication number 20200066841
- Publication date Feb 27, 2020
- Intel Corporation
- Ashutosh Sagar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
- Publication number 20190363022
- Publication date Nov 28, 2019
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES
- Publication number 20190305112
- Publication date Oct 3, 2019
- Sairam SUBRAMANIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH G...
- Publication number 20190304971
- Publication date Oct 3, 2019
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING ENDCAP PLUGS
- Publication number 20190305111
- Publication date Oct 3, 2019
- Intel Corporation
- Sairam SUBRAMANIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
- Publication number 20170133276
- Publication date May 11, 2017
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
- Publication number 20160141212
- Publication date May 19, 2016
- Intel Corporation
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS
- Publication number 20150179785
- Publication date Jun 25, 2015
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USING MATERIALS WITH DIFFERENT ETCH RATES TO FILL TRENCHES IN SEMIC...
- Publication number 20150179567
- Publication date Jun 25, 2015
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM TO CONTROL POLISH RATE VARIATION INTRODUCED BY DE...
- Publication number 20150179469
- Publication date Jun 25, 2015
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANNEALING A SACRIFICIAL LAYER
- Publication number 20140011373
- Publication date Jan 9, 2014
- Aravind Killampalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Temperature measurement with reduced extraneous infrared in a proce...
- Publication number 20090323759
- Publication date Dec 31, 2009
- Sridhar Govindaraju
- G01 - MEASURING TESTING
Information Patent Application
SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES
- Publication number 20090325392
- Publication date Dec 31, 2009
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS
- Publication number 20080242117
- Publication date Oct 2, 2008
- Panchapakesan Ramanarayanan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to reduce junction leakage through partial regrowth with ult...
- Publication number 20080121882
- Publication date May 29, 2008
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Implant and anneal amorphization process
- Publication number 20070099404
- Publication date May 3, 2007
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS

Sridhar S. Govindaraju

Person

Patents Grantslast 30 patents

Techniques and configurations to reduce transistor gate short defects

Non-planar semiconductor device having conforming ohmic contacts

Techniques and configurations to reduce transistor gate short defects

Self-aligned gate endcap (SAGE) architecture having local interconn...

Dual self-aligned gate endcap (SAGE) architectures

Unidirectional self-aligned gate endcap (SAGE) architectures with g...

Techniques and configurations to reduce transistor gate short defects

Self-aligned gate endcap (SAGE) architecture having endcap plugs

Unidirectional self-aligned gate endcap (SAGE) architectures with g...

Dual self-aligned gate endcap (SAGE) architectures

Techniques and configurations to reduce transistor gate short defects

Techniques and configurations to reduce transistor gate short defects

Techniques and configurations to reduce transistor gate short defects

Using materials with different etch rates to fill trenches in semic...

Techniques and configurations to reduce transistor gate short defects

Sub-second annealing processes for semiconductor devices

Method to reduce junction leakage through partial regrowth with ult...

Temperature measurement with reduced extraneous infrared in a proce...

Patents Applicationslast 30 patents

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

DUAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES

UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH G...

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING LOCAL INTERCONN...

NON-PLANAR SEMICONDUCTOR DEVICE HAVING CONFORMING OHMIC CONTACTS

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

DUAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES

UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH G...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING ENDCAP PLUGS

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS

USING MATERIALS WITH DIFFERENT ETCH RATES TO FILL TRENCHES IN SEMIC...

METHOD AND SYSTEM TO CONTROL POLISH RATE VARIATION INTRODUCED BY DE...

ANNEALING A SACRIFICIAL LAYER

Temperature measurement with reduced extraneous infrared in a proce...

SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES

APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS

Method to reduce junction leakage through partial regrowth with ult...

Implant and anneal amorphization process