Srihari Makineni

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Frequency scaling for per-core accelerator assignments
- Patent number 11,775,298
- Issue date Oct 3, 2023
- Intel Corporation
- Stephen T. Palermo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Platform slicing of central processing unit (CPU) resources
- Patent number 11,567,556
- Issue date Jan 31, 2023
- Intel Corporation
- Chris Macnamara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power efficient processor architecture
- Patent number 10,664,039
- Issue date May 26, 2020
- Intel Corporation
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet coalescing
- Patent number 10,652,147
- Issue date May 12, 2020
- Intel Corporation
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interrupt return instruction with embedded interrupt service functi...
- Patent number 10,095,520
- Issue date Oct 9, 2018
- Intel Corporation
- Zhen Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power efficient processor architecture
- Patent number 10,048,743
- Issue date Aug 14, 2018
- Intel Corporation
- Andrew J. Herdrich
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power efficient processor architecture
- Patent number 9,870,047
- Issue date Jan 16, 2018
- Intel Corporation
- Andrew J. Herdrich
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Power efficient processor architecture
- Patent number 9,864,427
- Issue date Jan 9, 2018
- Intel Corporation
- Andrew J. Herdrich
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Embedded branch prediction unit
- Patent number 9,753,732
- Issue date Sep 5, 2017
- Intel Corporation
- Xiaowei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient locking of memory pages
- Patent number 9,465,751
- Issue date Oct 11, 2016
- Intel Corporation
- Xiaowei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded branch prediction unit
- Patent number 9,395,994
- Issue date Jul 19, 2016
- Intel Corporation
- Xiaowei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt return instruction with embedded interrupt service functi...
- Patent number 9,378,164
- Issue date Jun 28, 2016
- Intel Corporation
- Zhen Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power efficient processor architecture
- Patent number 9,360,927
- Issue date Jun 7, 2016
- Intel Corporation
- Andrew J. Herdrich
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Differentiating cache reliability to reduce minimum on-die voltage
- Patent number 9,047,171
- Issue date Jun 2, 2015
- Intel Corporation
- Zhen Fang
- G11 - INFORMATION STORAGE
Information Patent Grant
Packet coalescing
- Patent number 8,718,096
- Issue date May 6, 2014
- Intel Corporation
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Quality of service implementation for platform resources
- Patent number 8,458,711
- Issue date Jun 4, 2013
- Intel Corporation
- Ramesh G. Illikkal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet coalescing
- Patent number 8,036,246
- Issue date Oct 11, 2011
- Intel Corporation
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing quality of service (QoS) for cache architectures using pr...
- Patent number 7,899,994
- Issue date Mar 1, 2011
- Intel Corporation
- Li Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache sharing based thread control
- Patent number 7,895,415
- Issue date Feb 22, 2011
- Intel Corporation
- Antonio Gonzalez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic quality of service (QoS) for a shared cache
- Patent number 7,725,657
- Issue date May 25, 2010
- Intel Corporation
- William C. Hasenplaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet coalescing
- Patent number 7,620,071
- Issue date Nov 17, 2009
- Intel Corporation
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Selective storage of data in levels of a cache memory
- Patent number 7,596,662
- Issue date Sep 29, 2009
- Intel Corporation
- Srihari Makineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectively inclusive cache architecture
- Patent number 7,552,288
- Issue date Jun 23, 2009
- Intel Corporation
- Ravishankar Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method and device for time slot status messaging among SONE...
- Patent number 7,525,989
- Issue date Apr 28, 2009
- Intel Corporation
- Linda Cline
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Sharing information between guests in a virtual machine environment
- Patent number 7,490,191
- Issue date Feb 10, 2009
- Intel Corporation
- Rameshkumar G. Illikkal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS
- Publication number 20240111531
- Publication date Apr 4, 2024
- Intel Corporation
- Stephen T. PALERMO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR WORKLOAD OPTIMIZED CENTRAL PROC...
- Publication number 20230217253
- Publication date Jul 6, 2023
- Intel Corporation
- Stephen Palermo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS
- Publication number 20210334101
- Publication date Oct 28, 2021
- Stephen T. Palermo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET COALESCING
- Publication number 20200328973
- Publication date Oct 15, 2020
- Intel Corporation
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PLATFORM SLICING OF CENTRAL PROCESSING UNIT (CPU) RESOURCES
- Publication number 20200225724
- Publication date Jul 16, 2020
- Intel Corporation
- Chris MACNAMARA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Efficient Processor Architecture
- Publication number 20180329478
- Publication date Nov 15, 2018
- Intel Corporation
- Andrew J. Herdrich
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PACKET COALESCING
- Publication number 20180198709
- Publication date Jul 12, 2018
- Intel Corporation
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PACKET COALESCING
- Publication number 20170048142
- Publication date Feb 16, 2017
- Intel Corporation
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
POWER EFFICIENT PROCESSOR ARCHITECTURE
- Publication number 20160306415
- Publication date Oct 20, 2016
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTI...
- Publication number 20160306630
- Publication date Oct 20, 2016
- Intel Corporation
- ZHEN FANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER EFFICIENT PROCESSOR ARCHITECTURE
- Publication number 20160299559
- Publication date Oct 13, 2016
- Intel Corporation
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER EFFICIENT PROCESSOR ARCHITECTURE
- Publication number 20160299558
- Publication date Oct 13, 2016
- Intel Corporation
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Embedded Branch Prediction Unit
- Publication number 20160283244
- Publication date Sep 29, 2016
- Intel Corporation
- Xiaowei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using Reduced Instruction Set Cores
- Publication number 20140258685
- Publication date Sep 11, 2014
- Srihari Makineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Reduced Instruction Set Core
- Publication number 20140223145
- Publication date Aug 7, 2014
- Intel Corporation
- Srihari Makineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIFFERENTIATING CACHE RELIABILITY TO REDUCE MINIMUM ON-DIE VOLTAGE
- Publication number 20140095799
- Publication date Apr 3, 2014
- Zhen Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Encoding to Increase Instruction Set Density
- Publication number 20140082334
- Publication date Mar 20, 2014
- Steven R. King
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Embedded Branch Prediction Unit
- Publication number 20140019736
- Publication date Jan 16, 2014
- Xiaowei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT LOCKING OF MEMORY PAGES
- Publication number 20130311738
- Publication date Nov 21, 2013
- Xiaowei Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER EFFICIENT PROCESSOR ARCHITECTURE
- Publication number 20130262902
- Publication date Oct 3, 2013
- Andrew J. Herdrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY
- Publication number 20120191896
- Publication date Jul 26, 2012
- Zhen Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET COALESCING
- Publication number 20110090920
- Publication date Apr 21, 2011
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packet coalescing
- Publication number 20100020819
- Publication date Jan 28, 2010
- Srihari Makineni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Resource-aware application scheduling
- Publication number 20090165004
- Publication date Jun 25, 2009
- Jaideep Moses
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT
- Publication number 20080244221
- Publication date Oct 2, 2008
- Donald K. Newell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic quality of service (QoS) for a shared cache
- Publication number 20080235457
- Publication date Sep 25, 2008
- William C. Hasenplaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache sharing based thread control
- Publication number 20080195849
- Publication date Aug 14, 2008
- Antonio Gonzalez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quality of service implementation for platform resources
- Publication number 20080075101
- Publication date Mar 27, 2008
- Ramesh G. Illikkal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sharing information between guests in a virtual machine environment
- Publication number 20080077765
- Publication date Mar 27, 2008
- Rameshkumar G. Illikkal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selective storage of data in levels of a cache memory
- Publication number 20080059707
- Publication date Mar 6, 2008
- Srihari Makineni
- G06 - COMPUTING CALCULATING COUNTING

Srihari Makineni

Person

Patents Grantslast 30 patents

Frequency scaling for per-core accelerator assignments

Platform slicing of central processing unit (CPU) resources

Power efficient processor architecture

Packet coalescing

Interrupt return instruction with embedded interrupt service functi...

Power efficient processor architecture

Power efficient processor architecture

Power efficient processor architecture

Embedded branch prediction unit

Efficient locking of memory pages

Embedded branch prediction unit

Interrupt return instruction with embedded interrupt service functi...

Power efficient processor architecture

Differentiating cache reliability to reduce minimum on-die voltage

Packet coalescing

Quality of service implementation for platform resources

Packet coalescing

Providing quality of service (QoS) for cache architectures using pr...

Cache sharing based thread control

Dynamic quality of service (QoS) for a shared cache

Packet coalescing

Selective storage of data in levels of a cache memory

Selectively inclusive cache architecture

System, method and device for time slot status messaging among SONE...

Sharing information between guests in a virtual machine environment

Patents Applicationslast 30 patents

FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS

SYSTEMS, METHODS, AND APPARATUS FOR WORKLOAD OPTIMIZED CENTRAL PROC...

FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS

PACKET COALESCING

PLATFORM SLICING OF CENTRAL PROCESSING UNIT (CPU) RESOURCES

Power Efficient Processor Architecture

PACKET COALESCING

PACKET COALESCING

POWER EFFICIENT PROCESSOR ARCHITECTURE

INTERRUPT RETURN INSTRUCTION WITH EMBEDDED INTERRUPT SERVICE FUNCTI...

POWER EFFICIENT PROCESSOR ARCHITECTURE

POWER EFFICIENT PROCESSOR ARCHITECTURE

Embedded Branch Prediction Unit

Using Reduced Instruction Set Cores

Configurable Reduced Instruction Set Core

DIFFERENTIATING CACHE RELIABILITY TO REDUCE MINIMUM ON-DIE VOLTAGE

Encoding to Increase Instruction Set Density

Embedded Branch Prediction Unit

EFFICIENT LOCKING OF MEMORY PAGES

POWER EFFICIENT PROCESSOR ARCHITECTURE

CIRCUITRY TO SELECT, AT LEAST IN PART, AT LEAST ONE MEMORY

PACKET COALESCING

Packet coalescing

Resource-aware application scheduling

EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT

Dynamic quality of service (QoS) for a shared cache

Cache sharing based thread control

Quality of service implementation for platform resources

Sharing information between guests in a virtual machine environment

Selective storage of data in levels of a cache memory