Srikanth T. Srinivasan

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Technologies for performing macro operations in memory
- Patent number 11,620,358
- Issue date Apr 4, 2023
- Intel Corporation
- Chetan Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for adaptable and efficient lane-wise tensor p...
- Patent number 11,379,229
- Issue date Jul 5, 2022
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for providing multiple tier memory media management
- Patent number 11,301,167
- Issue date Apr 12, 2022
- Intel Corporation
- Jawad B. Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for program order queue (POQ) to manag...
- Patent number 11,243,775
- Issue date Feb 8, 2022
- Intel Corporation
- Andrey Ayupov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for providing ECC pre-provisioning and handling for cr...
- Patent number 11,237,903
- Issue date Feb 1, 2022
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for symbolic store address generation...
- Patent number 11,188,341
- Issue date Nov 30, 2021
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for providing adaptive memory media management
- Patent number 11,182,158
- Issue date Nov 23, 2021
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for a hybrid reservation station for a...
- Patent number 11,126,438
- Issue date Sep 21, 2021
- Intel Corporation
- Srikanth Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for gang invariant operation optimizations usi...
- Patent number 11,093,250
- Issue date Aug 17, 2021
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for providing a scalable architecture for performing c...
- Patent number 11,080,226
- Issue date Aug 3, 2021
- Intel Corporation
- Shigeki Tomishima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for providing multiple levels of error correction
- Patent number 11,023,320
- Issue date Jun 1, 2021
- Intel Corporation
- Wei Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a multi-level reservation station with ins...
- Patent number 10,956,160
- Issue date Mar 23, 2021
- Intel Corporation
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a high throughput parallel co-processor an...
- Patent number 10,915,328
- Issue date Feb 9, 2021
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gather-scatter cache architecture having plurality of tag and data...
- Patent number 10,896,141
- Issue date Jan 19, 2021
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and method for data parallel single program multiple d...
- Patent number 10,831,505
- Issue date Nov 10, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for adaptable and efficient lane-wise tensor p...
- Patent number 10,776,110
- Issue date Sep 15, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for providing a scalable architecture for performing c...
- Patent number 10,534,747
- Issue date Jan 14, 2020
- Intel Corporation
- Shigeki Tomishima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for performing a calculation across a memory array
- Patent number 10,418,098
- Issue date Sep 17, 2019
- Intel Corporation
- Srikanth T. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduler implementing dependency matrix having restricted entries
- Patent number 10,235,180
- Issue date Mar 19, 2019
- Intel Corporation
- Srikanth T. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing dynamic portbinding within a...
- Patent number 9,904,553
- Issue date Feb 27, 2018
- Intel Corporation
- Bambang Sutanto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-retire scheme for tracking tentative accesses during transacti...
- Patent number 9,798,590
- Issue date Oct 24, 2017
- Intel Corporation
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for non-blocking register reclamation
- Patent number 9,652,236
- Issue date May 16, 2017
- Intel Corporation
- Srikanth T. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two level re-order buffer
- Patent number 9,495,159
- Issue date Nov 15, 2016
- Intel Corporation
- Mark J. Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing dynamic portbinding within a...
- Patent number 9,372,698
- Issue date Jun 21, 2016
- Intel Corporation
- Bambang Sutanto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced loop streaming detector to drive logic optimization
- Patent number 9,354,875
- Issue date May 31, 2016
- Intel Corporation
- Matthew C. Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical section detection and prediction mechanism for hardware lo...
- Patent number 9,262,173
- Issue date Feb 16, 2016
- Intel Corporation
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Store address prediction for memory disambiguation in a processing...
- Patent number 9,244,827
- Issue date Jan 26, 2016
- Intel Corporation
- Ho-Seop Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integration of processor and input/output hub
- Patent number 8,850,250
- Issue date Sep 30, 2014
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Limiting false wakeups of computing device components coupled via l...
- Patent number 8,812,878
- Issue date Aug 19, 2014
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic and idle power reduction sequence using recombinant clock a...
- Patent number 8,782,456
- Issue date Jul 15, 2014
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
System, Apparatus And Method For A Hybrid Reservation Station For A...
- Publication number 20200409710
- Publication date Dec 31, 2020
- Srikanth Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...
- Publication number 20200364045
- Publication date Nov 19, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A MULTI-LEVEL RESERVATION STATION WITH INS...
- Publication number 20200310801
- Publication date Oct 1, 2020
- Mark Dechene
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Symbolic Store Address Generation...
- Publication number 20200310817
- Publication date Oct 1, 2020
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gather-Scatter Cache Architecture For Single Program Multiple Data...
- Publication number 20200310992
- Publication date Oct 1, 2020
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Program Order Queue (POQ) To Manag...
- Publication number 20200310815
- Publication date Oct 1, 2020
- Intel Corporation
- Andrey Ayupov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING A SCALABLE ARCHITECTURE FOR PERFORMING C...
- Publication number 20200311019
- Publication date Oct 1, 2020
- Intel Corporation
- Shigeki Tomishima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A HIGH THROUGHPUT PARALLEL CO-PROCESSOR AN...
- Publication number 20200192676
- Publication date Jun 18, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...
- Publication number 20200104126
- Publication date Apr 2, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND METHOD FOR DATA PARALLEL SINGLE PROGRAM MULTIPLE D...
- Publication number 20200104139
- Publication date Apr 2, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING ERROR CORRECTION FOR ROW DIRECTION AND C...
- Publication number 20190317857
- Publication date Oct 17, 2019
- Intel Corporation
- Jawad B. Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING ECC PRE-PROVISIONING AND HANDLING FOR CR...
- Publication number 20190310911
- Publication date Oct 10, 2019
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING ADAPTIVE MEMORY MEDIA MANAGEMENT
- Publication number 20190272173
- Publication date Sep 5, 2019
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING MULTIPLE TIER MEMORY MEDIA MANAGEMENT
- Publication number 20190272121
- Publication date Sep 5, 2019
- Intel Corporation
- Jawad B. Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PERFORMING MACRO OPERATIONS IN MEMORY
- Publication number 20190266219
- Publication date Aug 29, 2019
- Intel Corporation
- Chetan Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING A SCALABLE ARCHITECTURE FOR PERFORMING C...
- Publication number 20190227981
- Publication date Jul 25, 2019
- Intel Corporation
- Shigeki Tomishima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PERFORMING TENSOR OPERATIONS IN MEMORY
- Publication number 20190227750
- Publication date Jul 25, 2019
- Intel Corporation
- Srikanth Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING MULTIPLE LEVELS OF ERROR CORRECTION
- Publication number 20190227871
- Publication date Jul 25, 2019
- Intel Corporation
- Wei Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR PROVIDING HIGH EFFICIENCY COMPUTE ARCHITECTURE ON...
- Publication number 20190228809
- Publication date Jul 25, 2019
- Intel Corporation
- Srikanth Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-POST RETIRE HYBRID HARDWARE LOCK ELISION (HLE) SCHEME
- Publication number 20190065160
- Publication date Feb 28, 2019
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR GANG INVARIANT OPERATION OPTIMIZATIONS
- Publication number 20190042269
- Publication date Feb 7, 2019
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR PERFORMING A CALCULATION ACROSS A MEMORY ARRAY
- Publication number 20190043572
- Publication date Feb 7, 2019
- Intel Corporation
- SRIKANTH T. SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-RETIRE SCHEME FOR TRACKING TENTATIVE ACCESSES DURING TRANSACTI...
- Publication number 20180011748
- Publication date Jan 11, 2018
- Intel Corporation
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING DYNAMIC PORTBINDING WITHIN A...
- Publication number 20170024213
- Publication date Jan 26, 2017
- Intel Corporation
- Bambang SUTANTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Non-Blocking Register Reclamation
- Publication number 20150178077
- Publication date Jun 25, 2015
- SRIKANTH T. SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO LEVEL RE-ORDER BUFFER
- Publication number 20150095627
- Publication date Apr 2, 2015
- Mark J. DECHENE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORE ADDRESS PREDICTION FOR MEMORY DISAMBIGUATION IN A PROCESSING...
- Publication number 20150089186
- Publication date Mar 26, 2015
- Ho-Seop Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING DYNAMIC PORTBINDING WITHIN A...
- Publication number 20150007188
- Publication date Jan 1, 2015
- Bambang SUTANTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR
- Publication number 20140201505
- Publication date Jul 17, 2014
- Matthew C. Merten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION
- Publication number 20140189306
- Publication date Jul 3, 2014
- Matthew C. Merten
- G06 - COMPUTING CALCULATING COUNTING

Srikanth T. Srinivasan

Person

Patents Grantslast 30 patents

Technologies for performing macro operations in memory

Apparatus and method for adaptable and efficient lane-wise tensor p...

Technologies for providing multiple tier memory media management

System, apparatus and method for program order queue (POQ) to manag...

Technologies for providing ECC pre-provisioning and handling for cr...

System, apparatus and method for symbolic store address generation...

Technologies for providing adaptive memory media management

System, apparatus and method for a hybrid reservation station for a...

Apparatus and method for gang invariant operation optimizations usi...

Technologies for providing a scalable architecture for performing c...

Technologies for providing multiple levels of error correction

Method and apparatus for a multi-level reservation station with ins...

Apparatus and method for a high throughput parallel co-processor an...

Gather-scatter cache architecture having plurality of tag and data...

Architecture and method for data parallel single program multiple d...

Apparatus and method for adaptable and efficient lane-wise tensor p...

Technologies for providing a scalable architecture for performing c...

Methods and systems for performing a calculation across a memory array

Scheduler implementing dependency matrix having restricted entries

Method and apparatus for implementing dynamic portbinding within a...

Post-retire scheme for tracking tentative accesses during transacti...

Instruction and logic for non-blocking register reclamation

Two level re-order buffer

Method and apparatus for implementing dynamic portbinding within a...

Enhanced loop streaming detector to drive logic optimization

Critical section detection and prediction mechanism for hardware lo...

Store address prediction for memory disambiguation in a processing...

Integration of processor and input/output hub

Limiting false wakeups of computing device components coupled via l...

Dynamic and idle power reduction sequence using recombinant clock a...

Patents Applicationslast 30 patents

System, Apparatus And Method For A Hybrid Reservation Station For A...

APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...

METHOD AND APPARATUS FOR A MULTI-LEVEL RESERVATION STATION WITH INS...

System, Apparatus And Method For Symbolic Store Address Generation...

Gather-Scatter Cache Architecture For Single Program Multiple Data...

System, Apparatus And Method For Program Order Queue (POQ) To Manag...

TECHNOLOGIES FOR PROVIDING A SCALABLE ARCHITECTURE FOR PERFORMING C...

APPARATUS AND METHOD FOR A HIGH THROUGHPUT PARALLEL CO-PROCESSOR AN...

APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...

ARCHITECTURE AND METHOD FOR DATA PARALLEL SINGLE PROGRAM MULTIPLE D...

TECHNOLOGIES FOR PROVIDING ERROR CORRECTION FOR ROW DIRECTION AND C...

TECHNOLOGIES FOR PROVIDING ECC PRE-PROVISIONING AND HANDLING FOR CR...

TECHNOLOGIES FOR PROVIDING ADAPTIVE MEMORY MEDIA MANAGEMENT

TECHNOLOGIES FOR PROVIDING MULTIPLE TIER MEMORY MEDIA MANAGEMENT

TECHNOLOGIES FOR PERFORMING MACRO OPERATIONS IN MEMORY

TECHNOLOGIES FOR PROVIDING A SCALABLE ARCHITECTURE FOR PERFORMING C...

TECHNOLOGIES FOR PERFORMING TENSOR OPERATIONS IN MEMORY

TECHNOLOGIES FOR PROVIDING MULTIPLE LEVELS OF ERROR CORRECTION

TECHNOLOGIES FOR PROVIDING HIGH EFFICIENCY COMPUTE ARCHITECTURE ON...

PRE-POST RETIRE HYBRID HARDWARE LOCK ELISION (HLE) SCHEME

APPARATUS AND METHOD FOR GANG INVARIANT OPERATION OPTIMIZATIONS

METHODS AND SYSTEMS FOR PERFORMING A CALCULATION ACROSS A MEMORY ARRAY

POST-RETIRE SCHEME FOR TRACKING TENTATIVE ACCESSES DURING TRANSACTI...

METHOD AND APPARATUS FOR IMPLEMENTING DYNAMIC PORTBINDING WITHIN A...

Instruction and Logic for Non-Blocking Register Reclamation

TWO LEVEL RE-ORDER BUFFER

STORE ADDRESS PREDICTION FOR MEMORY DISAMBIGUATION IN A PROCESSING...

METHOD AND APPARATUS FOR IMPLEMENTING DYNAMIC PORTBINDING WITHIN A...

PREDICTION-BASED THREAD SELECTION IN A MULTITHREADING PROCESSOR

ENHANCED LOOP STREAMING DETECTOR TO DRIVE LOGIC OPTIMIZATION