Srinath Sridharan

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Inter-PLL communication in a multi-PLL environment
- Patent number 12,261,609
- Issue date Mar 25, 2025
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Srinath Sridharan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Generating divided signals from phase-locked loop (PLL) output when...
- Patent number 12,149,255
- Issue date Nov 19, 2024
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Generating divided signals from phase-locked loop (PLL) output when...
- Patent number 11,967,965
- Issue date Apr 23, 2024
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast switching of output frequency of a phase locked loop (PLL)
- Patent number 11,923,864
- Issue date Mar 5, 2024
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Srinath Sridharan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Obtaining lock in a phase-locked loop (PLL) upon being out of phase...
- Patent number 11,588,489
- Issue date Feb 21, 2023
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Rakesh Kumar Gupta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Relocking a phase locked loop upon cycle slips between input and fe...
- Patent number 10,892,765
- Issue date Jan 12, 2021
- AURA SEMICONDUCTOR PVT. LTD
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hitless switching when generating an output clock derived from mult...
- Patent number 10,514,720
- Issue date Dec 24, 2019
- AURA SEMICONDUCTOR PVT. LTD
- Raja Prabhu J
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing errors due to non-linearities caused by a phase frequency...
- Patent number 9,742,414
- Issue date Aug 22, 2017
- AURA SEMICONDUCTOR PVT. LTD
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pop-up noise suppression in audio
- Patent number 9,277,315
- Issue date Mar 1, 2016
- ST-Ericsson SA
- Sanjeev Ranganathan
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Isolation and protection circuit for a receiver in a wireless commu...
- Patent number 9,124,354
- Issue date Sep 1, 2015
- ST-Ericsson SA
- Ramkishore Ganti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-standard transceiver architecture with common balun and mixer
- Patent number 8,892,159
- Issue date Nov 18, 2014
- ST-Ericsson SA
- Ramkishore Ganti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Coupling of speakers with integrated circuit
- Patent number 8,787,588
- Issue date Jul 22, 2014
- ST-Ericsson SA
- Sanjeev Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pop-up noise suppression in audio
- Patent number 8,787,597
- Issue date Jul 22, 2014
- ST-Ericsson India Pvt. Ltd.
- Sanjeev Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generation of a low jitter clock signal
- Patent number 8,085,080
- Issue date Dec 27, 2011
- ST-Ericsson SA
- Srinath Sridharan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...
- Publication number 20240154617
- Publication date May 9, 2024
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...
- Publication number 20230136353
- Publication date May 4, 2023
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FAST SWITCHING OF OUTPUT FREQUENCY OF A PHASE LOCKED LOOP (PLL)
- Publication number 20230122081
- Publication date Apr 20, 2023
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Srinath Sridharan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HITLESS SWITCHING WHEN GENERATING AN OUTPUT CLOCK DERIVED FROM MULT...
- Publication number 20190384351
- Publication date Dec 19, 2019
- Aura Semiconductor Pvt. Ltd.
- Raja Prabhu J
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE LOCKED LOOP WITH LOW PHASE-NOISE
- Publication number 20160336923
- Publication date Nov 17, 2016
- Aura Semiconductor Pvt. Ltd.
- ANKIT SEEDHER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCING ERRORS DUE TO NON-LINEARITIES CAUSED BY A PHASE FREQUENCY...
- Publication number 20160329902
- Publication date Nov 10, 2016
- Aura Semiconductor Pvt. Ltd.
- RAJA PRABHU J.
- G01 - MEASURING TESTING
Information Patent Application
POP-UP NOISE SUPPRESSION IN AUDIO
- Publication number 20140334632
- Publication date Nov 13, 2014
- SANJEEV RANGANATHAN
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Application
Multi-Standard Transceiver Architecture with Common Balun and Mixer
- Publication number 20130116005
- Publication date May 9, 2013
- Ramkishore Ganti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Isolation and Protection Circuit for a Receiver in a Wireless Commu...
- Publication number 20120287969
- Publication date Nov 15, 2012
- Ramkishore Ganti
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
POP-UP NOISE SUPPRESSION IN AUDIO
- Publication number 20100220875
- Publication date Sep 2, 2010
- ST-Ericsson India Pvt Ltd.
- Sanjeev Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
GENERATION OF A LOW JITTER CLOCK SIGNAL
- Publication number 20100219871
- Publication date Sep 2, 2010
- ST-Ericsson India Pvt Ltd.
- Srinath Sridharan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COUPLING OF SPEAKERS WITH INTEGRATED CIRCUIT
- Publication number 20100220868
- Publication date Sep 2, 2010
- ST-Ericsson India Pvt Ltd.
- Sanjeev Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Srinath Sridharan

Person

Patents Grantslast 30 patents

Inter-PLL communication in a multi-PLL environment

Generating divided signals from phase-locked loop (PLL) output when...

Generating divided signals from phase-locked loop (PLL) output when...

Fast switching of output frequency of a phase locked loop (PLL)

Obtaining lock in a phase-locked loop (PLL) upon being out of phase...

Relocking a phase locked loop upon cycle slips between input and fe...

Hitless switching when generating an output clock derived from mult...

Reducing errors due to non-linearities caused by a phase frequency...

Pop-up noise suppression in audio

Isolation and protection circuit for a receiver in a wireless commu...

Multi-standard transceiver architecture with common balun and mixer

Coupling of speakers with integrated circuit

Pop-up noise suppression in audio

Generation of a low jitter clock signal

Patents Applicationslast 30 patents

GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...

GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...

FAST SWITCHING OF OUTPUT FREQUENCY OF A PHASE LOCKED LOOP (PLL)

HITLESS SWITCHING WHEN GENERATING AN OUTPUT CLOCK DERIVED FROM MULT...

PHASE LOCKED LOOP WITH LOW PHASE-NOISE

REDUCING ERRORS DUE TO NON-LINEARITIES CAUSED BY A PHASE FREQUENCY...

POP-UP NOISE SUPPRESSION IN AUDIO

Multi-Standard Transceiver Architecture with Common Balun and Mixer

Isolation and Protection Circuit for a Receiver in a Wireless Commu...

POP-UP NOISE SUPPRESSION IN AUDIO

GENERATION OF A LOW JITTER CLOCK SIGNAL

COUPLING OF SPEAKERS WITH INTEGRATED CIRCUIT