Srinivasa Raghavan Sridhara

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Testing retention mode of an SRAM array
- Patent number 9,997,255
- Issue date Jun 12, 2018
- Texas Instruments Incorporated
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Grant
Power gate for latch-up prevention
- Patent number 9,646,680
- Issue date May 9, 2017
- Texas Instruments Incorporated
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic latch-up prevention in SRAM
- Patent number 9,496,024
- Issue date Nov 15, 2016
- Texas Instruments Incorporated
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Grant
Power gate for latch-up prevention
- Patent number 9,311,989
- Issue date Apr 12, 2016
- Texas Instruments Incorporated
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Grant
Initializing dummy bits of an SRAM tracking circuit
- Patent number 9,236,096
- Issue date Jan 12, 2016
- Texas Instruments Incorporated
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing signal development on a bit line in an SRAM
- Patent number 9,001,568
- Issue date Apr 7, 2015
- Texas Instruments Incorporated
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Grant
Channel hot carrier tolerant tracking circuit for signal developmen...
- Patent number 8,942,049
- Issue date Jan 27, 2015
- Texas Instruments Incorporated
- Srinivasa Sridhara
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power operation of static memory in a read-only mode
- Patent number 7,817,490
- Issue date Oct 19, 2010
- Texas Instruments Incorporated
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Power Gate for Latch-Up Prevention
- Publication number 20160189768
- Publication date Jun 30, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Application
POWER GATE FOR LATCH-UP PREVENTION
- Publication number 20160019945
- Publication date Jan 21, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING SIGNAL DEVELOPMENT ON A BIT LINE IN AN SRAM
- Publication number 20150213883
- Publication date Jul 30, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Application
CHANNEL HOT CARRIER TOLERANT TRACKING CIRCUIT FOR SIGNAL DEVELOPMEN...
- Publication number 20140078806
- Publication date Mar 20, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Sridhara
- G11 - INFORMATION STORAGE
Information Patent Application
INITIALIZING DUMMY BITS OF AN SRAM TRACKING CIRCUIT
- Publication number 20140071735
- Publication date Mar 13, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING SIGNAL DEVELOPMENT ON A BIT LINE IN AN SRAM
- Publication number 20140071736
- Publication date Mar 13, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING RETENTION MODE OF AN SRAM ARRAY
- Publication number 20140036609
- Publication date Feb 6, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit With Low Power SRAM
- Publication number 20120026808
- Publication date Feb 2, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Theodore W. Houston
- G11 - INFORMATION STORAGE
Information Patent Application
Low-Power Operation of Static Memory in a Read-Only Mode
- Publication number 20100260000
- Publication date Oct 14, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasa Raghavan Sridhara
- G11 - INFORMATION STORAGE

Srinivasa Raghavan Sridhara

Person

Patents Grantslast 30 patents

Testing retention mode of an SRAM array

Power gate for latch-up prevention

Automatic latch-up prevention in SRAM

Power gate for latch-up prevention

Initializing dummy bits of an SRAM tracking circuit

Testing signal development on a bit line in an SRAM

Channel hot carrier tolerant tracking circuit for signal developmen...

Low-power operation of static memory in a read-only mode

Patents Applicationslast 30 patents

Power Gate for Latch-Up Prevention

POWER GATE FOR LATCH-UP PREVENTION

TESTING SIGNAL DEVELOPMENT ON A BIT LINE IN AN SRAM

CHANNEL HOT CARRIER TOLERANT TRACKING CIRCUIT FOR SIGNAL DEVELOPMEN...

INITIALIZING DUMMY BITS OF AN SRAM TRACKING CIRCUIT

TESTING SIGNAL DEVELOPMENT ON A BIT LINE IN AN SRAM

TESTING RETENTION MODE OF AN SRAM ARRAY

Integrated Circuit With Low Power SRAM

Low-Power Operation of Static Memory in a Read-Only Mode