Srinivasan Chakravarthi

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low stress sacrificial cap layer
- Patent number 9,048,180
- Issue date Jun 2, 2015
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen based implants for defect reduction in strained silicon
- Patent number 8,084,312
- Issue date Dec 27, 2011
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low stress sacrificial cap layer
- Patent number 7,994,073
- Issue date Aug 9, 2011
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Phosphorus activated NMOS using SiC process
- Patent number 7,902,576
- Issue date Mar 8, 2011
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Antimony ion implantation for semiconductor components
- Patent number 7,795,122
- Issue date Sep 14, 2010
- Texas Instruments Incorporated
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Growth of unfaceted SiGe in MOS transistor fabrication
- Patent number 7,786,518
- Issue date Aug 31, 2010
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen based implants for defect reduction in strained silicon
- Patent number 7,670,892
- Issue date Mar 2, 2010
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor doping with improved activation
- Patent number 7,572,716
- Issue date Aug 11, 2009
- Texas Instruments Incorporated
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recess etch for epitaxial SiGe
- Patent number 7,553,717
- Issue date Jun 30, 2009
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a transistor device having an improved bre...
- Patent number 7,371,648
- Issue date May 13, 2008
- Texas Instruments Incorporated
- Jihong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interface improvement by stress application during oxide growth thr...
- Patent number 7,208,380
- Issue date Apr 24, 2007
- Texas Instruments Incorporated
- Anand T. Krishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Phosphorus activated NMOS using SiC process
- Patent number 7,179,696
- Issue date Feb 20, 2007
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme to improve NMOS with poly cap while mitigating P...
- Patent number 7,129,127
- Issue date Oct 31, 2006
- Texas Instruments Incorporated
- Periannan Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for improved dopant profiles in CMOS transistors
- Patent number 7,118,977
- Issue date Oct 10, 2006
- Texas Instruments Incorporated
- PR Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of abrupt ultra-shallow junctions
- Patent number 7,112,516
- Issue date Sep 26, 2006
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming a retrograde well in a transistor to enhance performance of...
- Patent number 7,061,058
- Issue date Jun 13, 2006
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having optimized shallow junction geometries a...
- Patent number 7,033,879
- Issue date Apr 25, 2006
- Texas Instruments Incorporated
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming a retrograde well in a transistor to enhance performance of...
- Patent number 6,927,137
- Issue date Aug 9, 2005
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of abrupt ultra-shallow junctions
- Patent number 6,852,603
- Issue date Feb 8, 2005
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of ultra shallow junctions from a solid source with flu...
- Patent number 6,849,528
- Issue date Feb 1, 2005
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate edge diode leakage reduction
- Patent number 6,847,089
- Issue date Jan 25, 2005
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device fabrication methods for inhibiting carbon out-...
- Patent number 6,830,980
- Issue date Dec 14, 2004
- Texas Instruments Incorporated
- Majid Movahed Mansoori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for improved mosfet drain extension activation
- Patent number 6,797,593
- Issue date Sep 28, 2004
- Texas Instruments Incorporated
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of abrupt ultra-shallow junctions using angled PAI and...
- Patent number 6,682,980
- Issue date Jan 27, 2004
- Texas Instruments Incorporated
- P. R. Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Phosphorus Activated NMOS Using SiC Process
- Publication number 20110212584
- Publication date Sep 1, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nitrogen Based Implants for Defect Reduction in Strained Silicon
- Publication number 20100120215
- Publication date May 13, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan CHAKRAVARTHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Carbon-Doped Epitaxial SiGe
- Publication number 20100038727
- Publication date Feb 18, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Recess Etch for Epitaxial SiGe
- Publication number 20090179236
- Publication date Jul 16, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GROWTH OF UNFACETED SIGE ALONG A SEMICONDUCTOR DEVICE WIDTH
- Publication number 20090166755
- Publication date Jul 2, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION SCHEMES TO AVOID FACETED SIGE
- Publication number 20090170270
- Publication date Jul 2, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANNEALING METHOD FOR SIGE PROCESS
- Publication number 20090170256
- Publication date Jul 2, 2009
- TEXAS INSTRUMENTS INCOPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Super Halo Formation Using a Reverse Flow for Halo Implants
- Publication number 20090152626
- Publication date Jun 18, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Ramesh Venugopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Phosphorus Activated NMOS Using SiC Process
- Publication number 20090142890
- Publication date Jun 4, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN NITROGEN...
- Publication number 20090050980
- Publication date Feb 26, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Shashank S. EKBOTE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methodology for Reducing Post Burn-In Vmin Drift
- Publication number 20090045472
- Publication date Feb 19, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
P-DOPED REGION WITH IMPROVED ABRUPTNESS
- Publication number 20080308904
- Publication date Dec 18, 2008
- TEXAS INSTRUMENTS INCORPORATED
- P. R. Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Recess Etch for Epitaxial SiGe
- Publication number 20080277699
- Publication date Nov 13, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DOPING WITH IMPROVED ACTIVATION
- Publication number 20080268623
- Publication date Oct 30, 2008
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Carbon-Doped Epitaxial SiGe
- Publication number 20080242032
- Publication date Oct 2, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Manufactured Using Passivation of Crystal Doma...
- Publication number 20080128821
- Publication date Jun 5, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Angelo Pinto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Stress Sacrificial Cap Layer
- Publication number 20080064175
- Publication date Mar 13, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A TRANSISTOR DEVICE HAVING AN IMPROVED BRE...
- Publication number 20080057654
- Publication date Mar 6, 2008
- Texas Instruments, Incorporated
- Jihong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING DIFFERENT SEMICONDUCTOR DEVICE TYPES WITH RED...
- Publication number 20070298574
- Publication date Dec 27, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Shashank S. Ekbote
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Stress Sacrificial Cap Layer
- Publication number 20070269951
- Publication date Nov 22, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Antimony ion implantation for semiconductor components
- Publication number 20070218662
- Publication date Sep 20, 2007
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nitrogen based implants for defect reduction in strained silicon
- Publication number 20070105294
- Publication date May 10, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Phosphorus Activated NMOS Using SiC Process
- Publication number 20070072383
- Publication date Mar 29, 2007
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Phosphorus Activated NMOS Using SiC Process
- Publication number 20070066024
- Publication date Mar 22, 2007
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for improved dopant profiles in CMOS transistors
- Publication number 20060099744
- Publication date May 11, 2006
- TEXAS INSTRUMENTS INCORPORATED
- PR Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integration scheme to improve NMOS with poly cap while mitigating P...
- Publication number 20060068541
- Publication date Mar 30, 2006
- PR Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Phosphorus activated NMOS using SiC process
- Publication number 20060060893
- Publication date Mar 23, 2006
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
N-type transistor with antimony-doped ultra shallow source and drain
- Publication number 20060017079
- Publication date Jan 26, 2006
- Srinivasan Chakravarthi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having optimized shallow junction geometries a...
- Publication number 20060001105
- Publication date Jan 5, 2006
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having optimized shallow junction geometries a...
- Publication number 20050245021
- Publication date Nov 3, 2005
- Texas Instruments, Incorporated
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS

Srinivasan Chakravarthi

Person

Patents Grantslast 30 patents

Low stress sacrificial cap layer

Nitrogen based implants for defect reduction in strained silicon

Low stress sacrificial cap layer

Phosphorus activated NMOS using SiC process

Antimony ion implantation for semiconductor components

Growth of unfaceted SiGe in MOS transistor fabrication

Nitrogen based implants for defect reduction in strained silicon

Semiconductor doping with improved activation

Recess etch for epitaxial SiGe

Method for manufacturing a transistor device having an improved bre...

Interface improvement by stress application during oxide growth thr...

Phosphorus activated NMOS using SiC process

Integration scheme to improve NMOS with poly cap while mitigating P...

System and method for improved dopant profiles in CMOS transistors

Fabrication of abrupt ultra-shallow junctions

Forming a retrograde well in a transistor to enhance performance of...

Semiconductor device having optimized shallow junction geometries a...

Forming a retrograde well in a transistor to enhance performance of...

Fabrication of abrupt ultra-shallow junctions

Fabrication of ultra shallow junctions from a solid source with flu...

Gate edge diode leakage reduction

Semiconductor device fabrication methods for inhibiting carbon out-...

Methods and apparatus for improved mosfet drain extension activation

Fabrication of abrupt ultra-shallow junctions using angled PAI and...

Patents Applicationslast 30 patents

Phosphorus Activated NMOS Using SiC Process

Nitrogen Based Implants for Defect Reduction in Strained Silicon

Carbon-Doped Epitaxial SiGe

Recess Etch for Epitaxial SiGe

GROWTH OF UNFACETED SIGE ALONG A SEMICONDUCTOR DEVICE WIDTH

INTEGRATION SCHEMES TO AVOID FACETED SIGE

ANNEALING METHOD FOR SIGE PROCESS

Super Halo Formation Using a Reverse Flow for Halo Implants

Phosphorus Activated NMOS Using SiC Process

METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN NITROGEN...

Methodology for Reducing Post Burn-In Vmin Drift

P-DOPED REGION WITH IMPROVED ABRUPTNESS

Recess Etch for Epitaxial SiGe

SEMICONDUCTOR DOPING WITH IMPROVED ACTIVATION

Carbon-Doped Epitaxial SiGe

Semiconductor Device Manufactured Using Passivation of Crystal Doma...

Low Stress Sacrificial Cap Layer

METHOD FOR MANUFACTURING A TRANSISTOR DEVICE HAVING AN IMPROVED BRE...

METHOD OF FABRICATING DIFFERENT SEMICONDUCTOR DEVICE TYPES WITH RED...

Low Stress Sacrificial Cap Layer

Antimony ion implantation for semiconductor components

Nitrogen based implants for defect reduction in strained silicon

Phosphorus Activated NMOS Using SiC Process

Phosphorus Activated NMOS Using SiC Process

System and method for improved dopant profiles in CMOS transistors

Integration scheme to improve NMOS with poly cap while mitigating P...

Phosphorus activated NMOS using SiC process

N-type transistor with antimony-doped ultra shallow source and drain

Semiconductor device having optimized shallow junction geometries a...

Semiconductor device having optimized shallow junction geometries a...