Patent Application
20080128821
The invention is directed, in general, to semiconductor devices and, more specifically, to semiconductor devices fabricated using passivation of unterminated bonds in an interfacial region associated with regions of different crystal orientation.
As the semiconductor industry continues to increase performance of integrated circuit devices in accordance with Moore's Law, physical limits of feature size are presenting new challenges to further improvement. For example, transistor gate lengths are approaching a value below which quantum effects cannot be neglected. Without new strategies, such challenges threaten to slow the rate of increase in device performance.
One such strategy involves increasing the mobility of minority charge carriers in a transistor so that the switching speed of the transistor may be increased without reducing the channel length of the transistor. A promising emerging technology dubbed “Hybrid Orientation Technology,” or HOT, involves producing localized, or “locally oriented” domains of crystal orientation on a semiconductor substrate. HOT relies on the principle that n-MOS transistors may operate faster on one orientation of a substrate, such as (100), while p-MOS transistors may operate faster on a different orientation, such as (110).
While some transistors formed on a HOT substrate may operate faster than they otherwise would, some device characteristics may be degraded. For example, some transistors formed in locally-oriented domains have been shown to exhibit higher leakage current from source/drain regions to the bulk substrate. Moreover, body contact from the transistors to the handle wafer may be non-ohmic. These effects may result in increase power dissipation and inadequate grounding of the integrated circuit.
Accordingly, what is needed in the art is a method of manufacturing transistors on a HOT substrate that reduces source/drain leakage and improves conduction across the interface between locally-oriented domains and the substrate.
To address the above-discussed deficiencies of the prior art, the invention provides in one embodiment a method of forming a semiconductor device. The method includes providing a semiconductor substrate including a bulk portion having a first crystal orientation, a top layer having a second different crystal orientation, and an interfacial region between the bulk portion and the top layer. Silicon or germanium is implanted into the top layer to form an amorphous portion. The amorphous portion is annealed to produce a recrystallized portion having the first crystal orientation. A passivating dopant is implanted into the interfacial region to passivate unterminated bonds within the interfacial region, thereby forming a passivated portion. A MOS transistor of a first type is formed at least partially in the recrystallized portion and a MOS transistor of a second type different from the first type is formed at least partially in the top layer.
Another embodiment is a method of forming a semiconductor device. The method includes providing a semiconductor substrate having a first portion and a second portion. The first portion has a crystal orientation, and the second portion is located over the first portion and has a different crystal orientation. An interfacial region is located between the first portion and second portion. A passivating dopant is implanted into the interfacial region to passivate unterminated bonds within the interfacial region.
Another embodiment is a semiconductor device. The semiconductor device has a first substrate with a crystal orientation, and a second substrate with a different crystal orientation located over the first substrate. An interfacial region exists between the first and second substrates. A passivating dopant is located within the interfacial region that passivates one or more unterminated bonds. A MOS transistor of a first type is located at least partially in the first substrate, and a MOS transistor of a second different type is located at least partially in the second substrate.
For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The invention recognizes that undesirable transistor characteristics associated with an interface between different crystal orientations of a hybrid-crystal orientation technology (HOT) substrate may be reduced by passivating unterminated bonds associated with lattice mismatch at the interface. Passivation may be accomplished, e.g., by implanting a passivating dopant that bonds to the unterminated bonds.
A HOT substrate typically includes a “handle wafer,” having one crystal orientation, and a “crystal-oriented” top layer having a different crystal orientation from the handle wafer. The bulk portion 1010 may be a handle wafer. Those skilled in the art appreciate that the crystal orientation of a wafer describes the crystalline face presented at the surface of the wafer. For example, a (100) silicon wafer presents the (100) face of the silicon lattice at the surface, while a (110) silicon wafer presents a (110) face of the lattice at the surface.
The crystal-oriented layer may be formed by a bonding technique such as direct silicon bond (DSB). Locally oriented domains may be formed in the top layer by causing selected portions of the crystal-oriented layer to become amorphous, i.e., lacking long-range crystalline ordering. For example, portions of the crystal-oriented layer may be masked, and unmasked portions may be made amorphous by implanting silicon or germanium. The amorphous portions may then be recrystallized by solid-phase epitaxy (SPE) using the handle wafer as a lattice template. Alternatively, selected portions of the crystal-oriented layer may be removed and replaced by a portion having the crystal orientation of the handle wafer by gas-phase epitaxy. In either case, the unaltered portions of the crystal-oriented layer are regarded as locally-oriented domains.
A HOT substrate may be obtained from a supplying source or formed conventionally. As used herein, the HOT substrate 1005 is “provided” when obtained from any source or formed by any currently existing or future discovered method. For brevity, the following discussion assumes that the HOT substrate is a silicon substrate, while recognizing that other semiconductors such as germanium may be used.
Without limitation,
The interface 1030 may be described by a plane between the lower lattice 1035 and the upper lattice 1040. However, the unterminated bonds are believed to diffuse several monolayers into the lower lattice 1035 and the upper lattice 1040 to reduce the energy of the lattice associated with strain. The portions of the lower and upper lattices 1035, 1040 that include unterminated bonds due to the lattice mismatch define an interfacial region 1050. In one embodiment, the location of the interface 1030 may be approximated as about midway between uppermost 1055 and lowermost 1060 atomic planes that experience deformation as a result of the lattice strain.
The unterminated bonds may trap charge carriers to produce a space-charge layer associated with the interfacial region 1050. As a result, I/V characteristics measured across the interface 1030 may display a non-ohmic conduction response. The non-ohmic response may interfere with good body contact in MOS devices. The space-charge layer may also result in increased leakage between the bulk portion 1010 and source/drain regions of MOS devices fabricated in the hybrid portions 1020.
These undesirable characteristics may advantageously be reduced by providing a chemical species to bond to the unterminated bonds 1045. When terminated, the bonds will typically not act as charge traps, conduction across the interface may be more ohmic, and associated transistor leakage may be reduced.
The passivating dopant is an atomic species extrinsic to the HOT substrate 1005 that, when implanted into a region containing an initial concentration of unterminated bonds, results in a decrease in the concentration of unterminated bonds. In one aspect, the passivating dopant may be a monovalent atomic species capable of forming a bond with the substrate atoms that is stable under ordinary operating conditions. Without limitation, hydrogen and fluorine are examples of such dopants. In some cases, a polyvalent atomic species may be used when that species may passivate multiple unterminated bonds, or when unterminated bonds associated with the polyvalent species may be in turn be passivated by another atomic species. For example, nitrogen may be used to passivate silicon unterminated bonds.
The implantation process 1070 may be performed using a semiconductor ion implantation tool. In some cases, the process may be designed to place a peak concentration of the passivating dopant within the interfacial region 1050. A dopant profile 1085 illustrates one position of the implanted dopant relative to the interface 1030.
By “within the interfacial region” it is meant that the interface 1030 is located within one standard deviation, σ, of a maximum concentration of the passivating dopant in the HOT substrate 1005. For example,
Specific conditions for implanting the passivating dopant are expected to depend on, e.g., the thickness T and crystal orientation of the hybrid portion 1020. Without limitation, the following example assumes the hybrid portion 1020 is (110) silicon with a thickness of about 150 nm. Fluorine may be implanted normal to the surface at an energy of about 53 keV and a surface dose of about 1014 cm−2. This implant is expected to produce a peak concentration of about 8·1018 cm−3 fluorine atoms about 150 nm below the surface of the HOT substrate 1005.
After implantation, the masking layer 1080 may be removed. In some embodiments, an anneal step may be performed to reduce lattice damage caused by the implantation, or to promote bonding of the passivating dopant to the unterminated bonds. If used, an anneal at a temperature ranging from about 950° C. and about 1025° C. for a period ranging from about 10 sec to about 30 sec is sufficient for these purposes. In other cases, an anneal after implanting the passivating dopant may be omitted, and an anneal associated with a later implantation process (source/drain, e.g.) may serve the purposes of the omitted anneal.
Advantageously, implantation of the passivating dopant may reduce leakage from p-MOS source/drain regions 1110 relative to the leakage present when the unterminated bonds in the interfacial region 1050 are not passivated. To illustrate, the example fluorine implant process recited above may result in a decrease of the reverse-bias leakage current of the source/drain regions 1110 of the p-MOS transistor 1105 to the n-well 1095 by about one order of magnitude or more.
In another embodiment, not shown, the passivating dopant may be implanted prior to formation of the isolation structure 1075. This ordering may be desirable to exploit efficiencies in a particular fabrication environment. If ordered in this manner, a similar benefit may be obtained as described above.
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The IC 300 may include MOS, BICMOS or bipolar components, and may further include passive components, such as capacitors, inductors or resistors. It may also include optical components or optoelectronic components. Those skilled in the art are familiar with these various types of components and their manufacture. The IC 300 may also be a dual-voltage IC, comprising transistors operating with difference threshold voltages.
Dielectric layers 370 are formed over the MOS transistors 350, 360, using currently known or later discovered methods. Interconnect structures 380 are located within the dielectric layers 370 to connect the various components, thus forming the integrated circuit 300. It will be apparent to one skilled in the art that several variations of the example interconnect architecture may be fabricated according to the invention with similarly advantageous results.
Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the invention.
