Stanley E. Schuster

Person

Granite Sprints, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive issue queue for reduced power at high performance
- Patent number 7,865,747
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Alper Buyuktosunoglu
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
eDRAM hierarchical differential sense AMP
- Patent number 7,821,858
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical 2T-DRAM with self-timed sensing
- Patent number 7,709,299
- Issue date May 4, 2010
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Interlocked synchronous pipeline clock gating
- Patent number 7,685,457
- Issue date Mar 23, 2010
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast, stable, SRAM cell using seven devices and hierarchical bit/se...
- Patent number 7,499,312
- Issue date Mar 3, 2009
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of stalling one or more stages in an interlocked synchronous...
- Patent number 7,475,227
- Issue date Jan 6, 2009
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical six-transistor SRAM
- Patent number 7,471,546
- Issue date Dec 30, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
eDRAM hierarchical differential sense amp
- Patent number 7,460,387
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Hierarchical 2T-DRAM with self-timed sensing
- Patent number 7,460,423
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Interlocked synchronous pipeline clock gating
- Patent number 7,308,593
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM hierarchical data path
- Patent number 7,289,369
- Issue date Oct 30, 2007
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor with low overhead predictive supply voltage gating for le...
- Patent number 7,134,028
- Issue date Nov 7, 2006
- International Business Machines Corporation
- Pradip Bose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with demand-driven clock throttling power reduction
- Patent number 7,076,681
- Issue date Jul 11, 2006
- International Business Machines Corporation
- Pradip Bose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interlocked synchronous pipeline clock gating
- Patent number 7,065,665
- Issue date Jun 20, 2006
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping and logic for combining L1 and L2 directories and/or arrays
- Patent number 6,981,096
- Issue date Dec 27, 2005
- International Business Machines Corporation
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for short range leakage control in pipelined c...
- Patent number 6,946,869
- Issue date Sep 20, 2005
- International Business Machines Corporation
- Hans M. Jacobson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous pipeline control interface using tag values to control...
- Patent number 6,925,549
- Issue date Aug 2, 2005
- International Business Machines Corporation
- Peter William Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous to asynchronous to synchronous interface
- Patent number 6,848,060
- Issue date Jan 25, 2005
- International Business Machines Corporation
- Peter W. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch structure for interlocked pipelined CMOS (IPCMOS) circuits
- Patent number 6,829,716
- Issue date Dec 7, 2004
- International Business Machines Corporation
- Peter W. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power circuit structures and methods for content addressable me...
- Patent number 6,608,771
- Issue date Aug 19, 2003
- International Business Machines Corporation
- Hans M. Jacobson
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit structures and methods for high-speed low-power select arbi...
- Patent number 6,512,397
- Issue date Jan 28, 2003
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interlocked pipelined CMOS
- Patent number 6,182,233
- Issue date Jan 30, 2001
- International Business Machines Corporation
- Stanley Everett Schuster
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for dual gate oxide dual workfunction CMOS
- Patent number 6,087,225
- Issue date Jul 11, 2000
- International Business Machines Corporation
- Gary Bela Bronner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cache reloading performance improvement through the use of early se...
- Patent number 6,081,872
- Issue date Jun 27, 2000
- International Business Machines Corporation
- Richard Edward Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trench capacitor structures
- Patent number 6,057,188
- Issue date May 2, 2000
- International Business Machines Corporation
- Badih El-Kareh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated processing and L2 DRAM cache
- Patent number 5,895,487
- Issue date Apr 20, 1999
- International Business Machines Corporation
- William Todd Boyd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic computer memory system having multiple width, high speed...
- Patent number 5,890,215
- Issue date Mar 30, 1999
- International Business Machines Corporation
- Richard E. Matick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trench capacitor structures
- Patent number 5,805,494
- Issue date Sep 8, 1998
- International Business Machines Corporation
- Badih El-Kareh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Controllable decoupling capacitor
- Patent number 5,770,969
- Issue date Jun 23, 1998
- International Business Machines Corporation
- Lloyd Andre Walls
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Virtual multi-port RAM employing multiple accesses during single ma...
- Patent number 5,542,067
- Issue date Jul 30, 1996
- International Business Machines Corporation
- Barbara A. Chappell
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
eDRAM Hierarchical Differential Sense AMP
- Publication number 20090080230
- Publication date Mar 26, 2009
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING
- Publication number 20080308941
- Publication date Dec 18, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR A DRAM CONCURRENT REFRESH ENGINE WITH PROCE...
- Publication number 20080270683
- Publication date Oct 30, 2008
- International Business Machines Corporation
- John E. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP
- Publication number 20080165601
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
Hierarchical 2T-DRAM with Self-Timed Sensing
- Publication number 20080165560
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
FAST, STABLE, SRAM CELL USING SEVEN DEVICES AND HIERARCHICAL BIT/SE...
- Publication number 20080165562
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
HIERARCHICAL SIX-TRANSISTOR SRAM
- Publication number 20080165561
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM HIERARCHICAL DATA PATH
- Publication number 20080016277
- Publication date Jan 17, 2008
- International Business Machines Corporation
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
INTERLOCKED SYNCHRONOUS PIPELINE CLOCK GATING
- Publication number 20070294548
- Publication date Dec 20, 2007
- International Business Machines Corperation
- Hans M. JACOBSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM hierarchical data path
- Publication number 20060233024
- Publication date Oct 19, 2006
- Richard E. Matick
- G11 - INFORMATION STORAGE
Information Patent Application
Interlocked synchronous pipeline clock gating
- Publication number 20060161795
- Publication date Jul 20, 2006
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interlocked synchronous pipeline clock gating
- Publication number 20060156046
- Publication date Jul 13, 2006
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and structure for short range leakage control in pipelined c...
- Publication number 20050083081
- Publication date Apr 21, 2005
- Hans M. Jacobson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Processor with low overhead predictive supply voltage gating for le...
- Publication number 20040221185
- Publication date Nov 4, 2004
- International Business Machines Corporation
- Pradip Bose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interlocked synchronous pipeline clock gating
- Publication number 20040068640
- Publication date Apr 8, 2004
- International Business Machines Corporation
- Hans M. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor with demand-driven clock throttling power reduction
- Publication number 20040044915
- Publication date Mar 4, 2004
- International Business Machines Corportation
- Pradip Bose
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER CIRCUIT STRUCTURES AND METHODS FOR CONTENT ADDRESSABLE ME...
- Publication number 20030043665
- Publication date Mar 6, 2003
- International Business Machines Corporation
- Hans M. Jacobson
- G11 - INFORMATION STORAGE
Information Patent Application
Synchronous to asynchronous to synchronous interface
- Publication number 20020120883
- Publication date Aug 29, 2002
- International Business Machines Corporation
- Peter W. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous pipeline control interface
- Publication number 20020083298
- Publication date Jun 27, 2002
- Peter William Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive issue queue for reduced power at high performance
- Publication number 20020053038
- Publication date May 2, 2002
- International Business Machines Corporation
- Alper Buyuktosunoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latch structure for interlocked pipelined CMOS (IPCMOS) circuits
- Publication number 20010056552
- Publication date Dec 27, 2001
- International Business Machines Corporation
- Peter W. Cook
- G06 - COMPUTING CALCULATING COUNTING

Stanley E. Schuster

Person

Patents Grantslast 30 patents

Adaptive issue queue for reduced power at high performance

eDRAM hierarchical differential sense AMP

Hierarchical 2T-DRAM with self-timed sensing

Interlocked synchronous pipeline clock gating

Fast, stable, SRAM cell using seven devices and hierarchical bit/se...

Method of stalling one or more stages in an interlocked synchronous...

Hierarchical six-transistor SRAM

eDRAM hierarchical differential sense amp

Hierarchical 2T-DRAM with self-timed sensing

Interlocked synchronous pipeline clock gating

DRAM hierarchical data path

Processor with low overhead predictive supply voltage gating for le...

Processor with demand-driven clock throttling power reduction

Interlocked synchronous pipeline clock gating

Mapping and logic for combining L1 and L2 directories and/or arrays

Method and structure for short range leakage control in pipelined c...

Asynchronous pipeline control interface using tag values to control...

Synchronous to asynchronous to synchronous interface

Latch structure for interlocked pipelined CMOS (IPCMOS) circuits

Low-power circuit structures and methods for content addressable me...

Circuit structures and methods for high-speed low-power select arbi...

Interlocked pipelined CMOS

Method for dual gate oxide dual workfunction CMOS

Cache reloading performance improvement through the use of early se...

Trench capacitor structures

Integrated processing and L2 DRAM cache

Electronic computer memory system having multiple width, high speed...

Trench capacitor structures

Controllable decoupling capacitor

Virtual multi-port RAM employing multiple accesses during single ma...

Patents Applicationslast 30 patents

eDRAM Hierarchical Differential Sense AMP

HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING

SYSTEMS AND METHODS FOR A DRAM CONCURRENT REFRESH ENGINE WITH PROCE...

eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP

Hierarchical 2T-DRAM with Self-Timed Sensing

FAST, STABLE, SRAM CELL USING SEVEN DEVICES AND HIERARCHICAL BIT/SE...

HIERARCHICAL SIX-TRANSISTOR SRAM

DRAM HIERARCHICAL DATA PATH

INTERLOCKED SYNCHRONOUS PIPELINE CLOCK GATING

DRAM hierarchical data path

Interlocked synchronous pipeline clock gating

Interlocked synchronous pipeline clock gating

Method and structure for short range leakage control in pipelined c...

Processor with low overhead predictive supply voltage gating for le...

Interlocked synchronous pipeline clock gating

Processor with demand-driven clock throttling power reduction

LOW-POWER CIRCUIT STRUCTURES AND METHODS FOR CONTENT ADDRESSABLE ME...

Synchronous to asynchronous to synchronous interface

Asynchronous pipeline control interface

Adaptive issue queue for reduced power at high performance

Latch structure for interlocked pipelined CMOS (IPCMOS) circuits