Stefan SLESAZECK

Person

Arnsdorf, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device structure having multiple gate terminals
- Patent number 11,515,428
- Issue date Nov 29, 2022
- NaMLab gGmbH
- Maik Simon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric memory and logic cell and operation method
- Patent number 11,205,467
- Issue date Dec 21, 2021
- NaMLab gGmbH
- Stefan Slesazeck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Artificial neuron based on ferroelectric circuit element
- Patent number 10,963,776
- Issue date Mar 30, 2021
- NaMLab gGmbH
- Halid Mulaosmanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polarization-based configurable logic gate
- Patent number 10,424,379
- Issue date Sep 24, 2019
- NaMLab gGmbH
- Stefan Slesazeck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilevel ferroelectric memory cell for an integrated circuit
- Patent number 10,043,567
- Issue date Aug 7, 2018
- NaMLab gGmbH
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Multilevel ferroelectric memory cell for an integrated circuit
- Patent number 9,830,969
- Issue date Nov 28, 2017
- NaMLab gGmbH
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Photodiode having a p-n junction with varying expansion of the spac...
- Patent number 8,946,617
- Issue date Feb 3, 2015
- NaMLab gGmbH
- Juergen Holz
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit comprising a thyristor and method of controlling...
- Patent number 7,940,558
- Issue date May 10, 2011
- Qimonda AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit and method of operating an integrated circuit
- Patent number 7,738,279
- Issue date Jun 15, 2010
- Qimonda AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell array comprising floating body memory cells
- Patent number 7,719,869
- Issue date May 18, 2010
- Qimonda AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device, an electronic device and a method for operati...
- Patent number 7,688,660
- Issue date Mar 30, 2010
- Qimonda AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit and method of manufacturing an integrated circuit
- Patent number 7,622,354
- Issue date Nov 24, 2009
- Qimonda AG
- Lars Dreeskornfeld
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell array and method of manufacturing the same
- Patent number 7,473,952
- Issue date Jan 6, 2009
- Infineon Technologies AG
- Dirk Manger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method for a recessed channel array transistor and co...
- Patent number 7,189,617
- Issue date Mar 13, 2007
- Infineon Technologies AG
- Stefan Slesazeck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Architecture and fabrication method of a vertical memory cell
- Patent number 7,064,373
- Issue date Jun 20, 2006
- Infineon Technologies AG
- Bernd Goebel
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURE HAVING MULTIPLE GATE TERMINALS
- Publication number 20210202752
- Publication date Jul 1, 2021
- NaMLab gGmbH
- Maik Simon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERROELECTRIC MEMORY AND LOGIC CELL AND OPERATION METHOD
- Publication number 20200357453
- Publication date Nov 12, 2020
- NaMLab gGmbH
- Stefan Slesazeck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARTIFICIAL NEURON BASED ON FERROELECTRIC CIRCUIT ELEMENT
- Publication number 20200065647
- Publication date Feb 27, 2020
- NaMLab gGmbH
- Halid MULAOSMANOVIC
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POLARIZATION-BASED CONFIGURABLE LOGIC GATE
- Publication number 20190172539
- Publication date Jun 6, 2019
- NaMLab gGmbH
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Application
Multilevel Ferroelectric Memory Cell for an Integrated Circuit
- Publication number 20180082729
- Publication date Mar 22, 2018
- NaMLab gGmbH
- Stefan SLESAZECK
- G11 - INFORMATION STORAGE
Information Patent Application
Multilevel Ferroelectric Memory Cell for an Integrated Circuit
- Publication number 20170162250
- Publication date Jun 8, 2017
- NaMLab gGmbH
- Stefan SLESAZECK
- G11 - INFORMATION STORAGE
Information Patent Application
PHOTODIODE, PHOTODIODE ARRAY AND METHOD OF OPERATION
- Publication number 20120286144
- Publication date Nov 15, 2012
- NaMLab GmbH
- Juergen Holz
- G01 - MEASURING TESTING
Information Patent Application
Ferroelectric Memory Cell Arrays and Method of Operating the Same
- Publication number 20100110753
- Publication date May 6, 2010
- QIMONDA AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor Device, an Electronic Device and a Method for Operati...
- Publication number 20100014372
- Publication date Jan 21, 2010
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit and Method of Operating an Integrated Circuit
- Publication number 20090296449
- Publication date Dec 3, 2009
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuit Comprising a Thyristor and Method of Controlling...
- Publication number 20090213648
- Publication date Aug 27, 2009
- QIMONDA AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Application
Floating Body Memory Cell with a Non-Overlapping Gate Electrode
- Publication number 20090179262
- Publication date Jul 16, 2009
- QIMONDA AG
- Juergen Holz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory Cell Array Comprising Floating Body Memory Cells
- Publication number 20090129145
- Publication date May 21, 2009
- QIMONDA AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
- Publication number 20090057778
- Publication date Mar 5, 2009
- Lars Dreeskornfeld
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE
- Publication number 20080308870
- Publication date Dec 18, 2008
- QIMONDA AG
- Juergen Faul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Manufacturing method for forming a recessed channel transistor, met...
- Publication number 20080299722
- Publication date Dec 4, 2008
- Jessica Hartwich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATI...
- Publication number 20080253179
- Publication date Oct 16, 2008
- QIMONDA AG
- Stefan Slesazeck
- G11 - INFORMATION STORAGE
Information Patent Application
Trench storage capacitor
- Publication number 20070034927
- Publication date Feb 15, 2007
- Harald Seidl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell array and method of manufacturing the same
- Publication number 20060244024
- Publication date Nov 2, 2006
- Dirk Manger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Manufacturing method for a recessed channel array transistor and co...
- Publication number 20060234451
- Publication date Oct 19, 2006
- Infineon Technologies AG
- Stefan Slesazeck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Architecture and fabrication method of a vertical memory cell
- Publication number 20050036392
- Publication date Feb 17, 2005
- Bernd Goebel
- H01 - BASIC ELECTRIC ELEMENTS

Stefan SLESAZECK

Person

Patents Grantslast 30 patents

Semiconductor device structure having multiple gate terminals

Ferroelectric memory and logic cell and operation method

Artificial neuron based on ferroelectric circuit element

Polarization-based configurable logic gate

Multilevel ferroelectric memory cell for an integrated circuit

Multilevel ferroelectric memory cell for an integrated circuit

Photodiode having a p-n junction with varying expansion of the spac...

Integrated circuit comprising a thyristor and method of controlling...

Integrated circuit and method of operating an integrated circuit

Memory cell array comprising floating body memory cells

Semiconductor device, an electronic device and a method for operati...

Integrated circuit and method of manufacturing an integrated circuit

Memory cell array and method of manufacturing the same

Manufacturing method for a recessed channel array transistor and co...

Architecture and fabrication method of a vertical memory cell

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE STRUCTURE HAVING MULTIPLE GATE TERMINALS

FERROELECTRIC MEMORY AND LOGIC CELL AND OPERATION METHOD

ARTIFICIAL NEURON BASED ON FERROELECTRIC CIRCUIT ELEMENT

POLARIZATION-BASED CONFIGURABLE LOGIC GATE

Multilevel Ferroelectric Memory Cell for an Integrated Circuit

Multilevel Ferroelectric Memory Cell for an Integrated Circuit

PHOTODIODE, PHOTODIODE ARRAY AND METHOD OF OPERATION

Ferroelectric Memory Cell Arrays and Method of Operating the Same

Semiconductor Device, an Electronic Device and a Method for Operati...

Integrated Circuit and Method of Operating an Integrated Circuit

Integrated Circuit Comprising a Thyristor and Method of Controlling...

Floating Body Memory Cell with a Non-Overlapping Gate Electrode

Memory Cell Array Comprising Floating Body Memory Cells

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

INTEGRATED CIRCUIT WITH A SPLIT FUNCTION GATE

Manufacturing method for forming a recessed channel transistor, met...

SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND A METHOD FOR OPERATI...

Trench storage capacitor

Memory cell array and method of manufacturing the same

Manufacturing method for a recessed channel array transistor and co...

Architecture and fabrication method of a vertical memory cell