BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a recessed channel transistor, a manufacturing method for forming a corresponding integrated semiconductor memory device, and to a corresponding self-aligned mask structure.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated semiconductor memory devices, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology, in particular, DRAM technology which is scaled down to below 100 nm generation and provides big challenges.
DRAM memory circuits of today usually comprise stripe-like active areas, e.g. fabricated in silicon, separated by STI insulation trenches filled with a dielectric material such as silicon oxide.
In trench capacitor DRAM memory circuits, along said stripe-like active areas, memory cell trench capacitors are arranged which are separated from each other by intervening memory cell transistor forming regions where the respective memory cell transistors are formed.
With feature sizes that are becoming smaller and smaller and nowadays are well below 100 nm, it becomes a challenging task to form mask openings for etching grooves for EUD (Extended U-Groove Device) transistors into the active area stripes between the memory cell capacitors in a manner which is reliable and reproducible in mass production.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method for forming a recessed channel transistor as claimed in claim 1 is provided.
According to a second aspect of the invention, a method for forming a recessed channel transistor as claimed in claim 11 is provided.
According to a third aspect of the invention, a manufacturing method for an integrated semiconductor memory device as claimed in claim 12 is provided.
According to a fifth aspect of the invention, a manufacturing method for an integrated semiconductor memory device as claimed in claim 27 is provided.
According to a sixth aspect of the invention, a manufacturing method for an integrated semiconductor memory device as claimed in claim 31 is provided.
According to a seventh aspect of the invention, a self-aligned mask structure for manufacturing an integrated semiconductor memory device as claimed in claim 37 is provided.
Further embodiments are listed in the respective dependent claims.
DESCRIPTION OF THE DRAWINGS
In the Figures:
FIG. 1A-J show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a first embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a);
FIG. 2A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a second embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a);
FIG. 3A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a third embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a);
FIG. 4A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a fourth embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a);
FIG. 5A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a fifth embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a);
FIG. 6A,B show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a sixth embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a); and
FIG. 7A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a seventh embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
In the Figures, identical reference signs denote equivalent or functionally equivalent components.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1A-J show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a first embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
In FIG. 1A, reference sign 1 denotes a silicon semiconductor substrate. Formed in said semiconductor substrate 1 is a plurality of memory cell trench capacitors C1-C12 along rows running in x-direction and along columns running in y-direction.
Said memory cell trench capacitors C1-C12 comprise in their upper regions an insulating collar 3 made of silicon oxide and an inner conductive electrode 4 made of polysilicon. The inner conductive electrodes 4 include a single-sided buried strap 2 for electrical connection to a memory cell transistor to be formed in memory cell transistor forming regions located between two adjacent memory cell trench capacitors. The diameter of the memory cell trench capacitors and the width of the intervening memory cell transistor forming regions in the substrate 1 equals d which in this example is the smallest feature size of the involved technology.
The plurality of memory cell trench capacitors C1-C12 has been formed using a first mask 5 made of silicon nitride provided on the upper surface OF of the substrate 1. The mask 5 includes openings 5a corresponding to the diameter d of said memory cell trench capacitors C1-C12.
The process state shown in FIG. 1A is the state immediately after selectively etching back a part of the inner conductive electrodes 4 in order to form said single-sided buried straps 2.
In a next process step which is illustrated in FIG. 1B, a silicon nitride liner 6 is deposited over the entire structure of FIG. 1A. Thereafter, a polysilicon layer is deposited over the nitride liner 6 and polished back in a chemical-mechanical polishing process such that it has the same upper level as the silicon nitride mask layer 5. Thus, the mask openings 5a are now filled with respective polysilicon infills 4a.
In a subsequent process step which is illustrated in FIG. 1C a silicon oxide hard mask 17 is deposited and patterned over the structure of FIG. 1B such that it has a plurality of stripes running in parallel along the x-direction and being separated from each other by a predetermined distance g which determines the width of insulation trenches to be formed in this process step.
Using said hard mask 17, first a nitride etch step and thereafter a silicon etch step are performed in order to define active area stripes and intervening insulation trenches running along the x-direction. FIG. 1D shows the process state immediately after the silicon etch step for the insulation trenches.
As depicted in FIG. 1E, the hard mask 17 is removed after the silicon etch step, and an oxide fill 9 is deposited such that it is planar with the upper surface of the nitride mask 5. Alternatively, the silicon oxide fill 9 could be deposited and polished back thereafter.
Now, the active area stripes AA1-AA4 and the intervening insulation trenches IT1-IT5 running along the x-direction are completed.
Thereafter, as shown in FIG. 1, the silicon nitride mask 5 is selectively removed in a nitride etch step. Then, spacers 4b made of polysilicon are formed around said remaining infills 4a which after the removal of the mask 5 protrude from the upper surface OF of the silicon semiconductor substrate 1. The spacers 4b are formed in a selective silicon epitaxial growth process which has the effect that they extend also in the height direction.
Thus, the spacers 4b laterally extend to beyond the trench openings defined by mask openings 5a and expose only a part of the memory cell transistor forming regions of a predetermined width d′. These exposed parts will later correspond to a region where respective grooves for the memory cell transistors are to be formed.
Generally, the formation of the grooves could also be performed in an immediately succeeding process step, however, in this first embodiment, the spacers 4b and infills 4a will be removed first in an intervening process step sequence.
As shown in FIG. 1G, another nitride mask 5′ is formed in the exposed parts of the memory cell transistor forming regions between the spacers 4b shown in FIG. 1F. This may easily be achieved by a nitride deposition and etch back or polish back process sequence. Thereafter, the polysilicon spacers 4b and infills 4a are removed in a selective silicon etch step. Then, another nitride liner 6′ is deposited over the entire structure which leads to the process state shown in FIG. 1G.
Thereafter, as shown in FIG. 1H an oxide fill 19 is provided which extends to the same upper level as the second nitride mask 5′. Thereafter, the second nitride mask 5′ is removed in a selective etch step.
The oxide fill 19 now forms a plurality of extension regions located above each of the plurality of memory cell trench capacitors C1-C12 on said surface OF which extension regions 19 expose said already above-mentioned part of said memory cell transistor forming regions of width d′ where the grooves of the EUD devices have to be formed.
In a next process step, which is shown in FIG. 11 said grooves 11 are formed in said memory cell transistor forming regions in a silicon etch step using said extension regions formed of oxide fill 19 as a mask.
As shown in FIG. 1J, a plurality of memory cell transistors T1-T4 is formed in said grooves 11 subsequently. Although not shown here, also an isotropic silicon etch step for widening said grooves 11 and an oxide etch step for corner device formation could be performed at this process state.
According to the shown first embodiment, a gate oxide layer 25 is formed in said grooves 11, then a polysilicon control electrode 25 is formed in the lower part of the grooves 11, then sidewall spacers 35 made of an insulating material such as silicon oxide are formed in the upper part of the grooves 11 on top of said polysilicon control electrode 25, and finally, a polysilicon contact layer 40 is deposited over the entire structure which leads to the process state shown in FIG. 1J.
As becomes immediately clear to the average skilled person, because well known in the art, the following process steps which are not illustrated here include the formation of word-lines by patterning the polysilicon contact layer 40 and the formation of bit-line contacts and bit-lines which are connected to the drains of the memory cell transistors T1-T5, the sources of which are connected to the memory cell capacitors C1-C12.
The first embodiment explained above provides a process sequence which allows the processing of the extended U-groove memory transistor devices in a self-adjusted manner with respect to the positions of the adjacent pairs of deep trench capacitors.
According to a not separately illustrated modification of the above described first embodiment, the polysilicon infills 4a are removed in the process state of FIG. 1E and replaced by corresponding carbon infills. Thereafter, the silicon nitride mask 5 is selectively removed in a nitride etch step. Then, spacers carbon made of carbon are formed around the remaining carbon infills which after the removal of the mask 5 protrude from the upper surface OF of the silicon semiconductor substrate 1.
Also, the modification could start in a process state where the polysilicon infills are provided above the surface OF, said trenches being filled with an insulating fill which extends up to the upper surface OF of the substrate 1 and partially surrounds the buried strap (cmp. FIG. 7A described below).
FIG. 2A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a second embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
The process state shown in FIG. 2A is obtained from the process state of FIG. 1A by depositing said nitride liner 6 over the entire structure of FIG. 1A.
In a next process step which is shown in FIG. 2B, a nitride pullback etch step is performed in order to isotropically remove a part of the nitride mask 5 from the upper surface OF of the substrate 1.
Thereafter, as shown in FIG. 2C, an insulating oxide fill 19′ is deposited which insulating fill 19′ extends to the same height as the etched back nitride mask layer 5.
Further, as may be obtained from FIG. 2D, the insulation trench IT1-IT5 forming steps as already explained with respect to FIG. 1C, 1D, 1E are performed, whereafter the remaining part of the nitride mask 5′ is removed in a selective etch step.
The oxide fill 19′ now forms a plurality of extension regions located above each of the plurality of memory cell trench capacitors C1-C12 on said surface OF which extension regions 19′ expose said already above-mentioned part of said memory cell transistor forming regions of width d′ where the grooves of the EUD devices have to be formed.
The process state shown in FIG. 2D corresponds to the process state shown in FIG. 1H, and therefore a repeated description of the remaining process steps will be omitted here.
FIG. 3A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a third embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
The process state shown in FIG. 3A originates from the process state shown in FIG. 1E after having performed a recess etch of the STI oxide fill layer 9. The depth of the recess corresponds to the height of the nitride mask layer 5.
In a subsequent process step which is shown in FIG. 3B the nitride mask 5 is removed in a selective etch step. Then, a nitride liner 6″ is deposited over the entire structure.
Subsequently, a TEOS spacer formation step is performed in order to form respective TEOS spacers 29 around the infills 4a which after the recess etch of the STI oxide fill layer 9 protrude from the upper surface OF of the substrate 1. After the spacer formation step, said part of said memory cell transistor forming regions of the predetermined width d′ is exposed.
Thereafter, as shown in FIG. 3C, a second nitride mask 5″ is formed between the spacers 29 by depositing and etching back a nitride layer. Subsequently, the polysilicon infills 4a are removed in a silicon etch step, whereafter the spacers 29 are removed in an oxide etch step.
Then, an insulating fill 42 made of silicon oxide is deposited and etched back so as to be planar with the upper surface OF of the substrate 1. In order to achieve the process state shown in FIG. 3C another nitride liner 6′″ is deposited over the entire structure. Thereafter, an oxide fill 19″ is provided which extends to the same upper level as the second nitride mask 5″.
As may be obtained from FIG. 3D, the second nitride mask 5″ is selectively removed in order to expose the part of the memory cell transistor forming region having the width d′ where the grooves for the memory cell transistor have to be formed in the following steps the explanation of which is omitted here because it has already been given with respect to FIGS. 1H-1J.
The oxide fill 19″ now forms a plurality of extension regions located above each of the plurality of memory cell trench capacitors C1-C12 on said surface OF which extension regions 19″ serve as a mask in the step of forming grooves of the EUD devices.
FIG. 4-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a fourth embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
The process state shown in FIG. 4A originates from the process state shown in FIG. 1E by performing a nitride recess etch step for recessing the nitride mask 5 and by performing a depositing step for depositing an oxide layer 49 over the entire structure.
Thereafter, as shown in FIG. 4B, the oxide layer 49 is recessed to the upper level of the polysilicon infills 4a. Then, a silicon etch step is performed for removing the polysilicon infills 4a, completely. Said silicon etch step stops on the nitride liner 6.
Further with reference to FIG. 4C, a nitride pullback etch step is performed under the remaining oxide layer 49 as a mask. Thereafter, the oxide layer 49 is completely removed. Finally, another nitride liner 6″″ is deposited over the entire structure which leads to the process state shown in FIG. 4C.
With reference to FIG. 4D, an oxide fill layer 19′″ is provided which extends to the same upper level as the etched back nitride mask layer 5. Then, the nitride mask layer is removed completely in a selective etch step. As to reach the process state shown in FIG. 4D which corresponds to the process step shown in FIG. 1H.
The oxide fill 19′″ now forms a plurality of extension regions located above each of the plurality of memory cell trench capacitors C1-C12 on said sur-face OF which extension regions 19′″ serve as a mask in the step of forming grooves of the EUD devices.
The remaining process steps will not be repeatedly described because this has already been done with respect to FIGS. 1I-1J above.
FIG. 5A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a fifth embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
The process step shown in FIG. 5A originates from the process step shown in FIG. 1E by selectively removing the polysilicon infills 4a in a corresponding silicon etch step which stops on the nitride liner 6.
Thereafter, as shown in FIG. 5B, a nitride pullback etch step is performed for removing a part of the nitride mask 5. The remaining part of the nitride mask 5 covers the part having the width d′ of the memory cell transistor forming region between adjacent memory cell trench capacitors.
As shown in FIG. 5C, the insulation trench oxide layer 9 is then selectively recessed to the level of the upper surface OF of the substrate 1, and then another nitride liner 6″″″ is deposited over the entire structure.
Then, as shown in FIG. 5D an oxide fill layer 19″″ is provided up to the level of the nitride mask layer 5 whereafter the nitride mask layer 5 is removed in a selective etch step so as to obtain the process state shown in FIG. 5D which corresponds to the process state shown in FIG. 1H.
The oxide fill 19″″ now forms a plurality of extension regions located above each of the plurality of memory cell trench capacitors C1-C12 on said surface OF which extension regions 19″″ serve as a mask in the step of forming grooves of the EUD devices.
The remaining steps correspond to the process steps already described with respect to FIGS. 1I-1J.
FIG. 6A,B show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a sixth embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
The process state shown in FIG. 6A is based on the process step shown in FIG. 1E and is obtained therefrom by recessing the insulating oxide layer 9 of the insulation trenches and by recessing the nitride mask 5 by the same height.
In a subsequent process step which is shown in FIG. 6B, polysilicon spacers 4b′ are formed around the polysilicon infills 4a which after the recess steps protrude from the surface of the nitride mask layer 5.
Thereafter, the nitride mask 5 is etched selectively using said polysilicon spacers 4b′ formed around said infills 4a as a mask in order to obtain the process state shown in FIG. 6B.
The thus obtained exposed part of the memory transistor forming region between two adjacent memory cell trench capacitors having the width d′ corresponds to the part where the groove for the memory cell transistor has to be etched using the infills 4a extended by the spacers 4b′ as a mask.
In this embodiment, the extension region is formed of the nitride mask 5, the polysilicon infills 4a, and the polysilicon spacers 4b′.
The remaining steps correspond to the process steps already described with respect to FIGS. 1I-1J.
FIG. 7A-D show schematic layouts for illustrating a manufacturing method for a recessed channel transistor in an integrated semiconductor memory device according to a seventh embodiment of the present invention, namely a) as plain view, b) as cross-section along line A-B of a), and c) as cross-section along line C-D of a).
The process state shown in FIG. 7A originates from the process state shown in FIG. 1E by selectively removing the polysilicon infills 4a and by depositing and etching back an insulating fill 7 which extends up to the upper surface OF of the substrate 1.
In a subsequent process step a polysilicon liner 40 is deposited over the entire structure and thereafter subjected to an ion implantation I which is directed perpendicular to the upper surface OF of the substrate 1, as may be obtained from FIG. 7A.
As a consequence of this implantation step, the horizontal implanted parts of the polysilicon liner 40 are much more resistant against a specific etching than the non-implanted parts along the verticals.
Consequently, it is possible to remove the vertical parts of the liner 40 along the nitride mask 5 in a selective etch step which is depicted in FIG. 7B.
Further with respect to FIG. 7C a nitride pullback etch step is performed so as to remove a part of the nitride mask 5 such that the remaining part of the nitride mask 5 corresponds to the part of the memory cell transistor forming region having width of d′ corresponding to the groove to be formed for the memory cell transistor.
Finally, with respect to FIG. 7D, another nitride liner 6″″″ is deposited over the entire structure, and thereafter an oxide fill layer 19″″″ is deposited up to the upper level of the nitride mask 5. Then, the nitride mask 5 is removed in a selective etch step so as to obtain the process state shown in FIG. 7D which corresponds to the process step shown in FIG. 1H.
The oxide fill 19′″″ now forms a plurality of extension regions located above each of the plurality of memory cell trench capacitors C1-C12 on said surface OF which extension regions 19′″″ serve as a mask in the step of forming grooves of the EUD devices.
The remaining process steps correspond to the process steps shown in FIGS. 1I, 1J already explained above.
Although the present invention has been described with reference to a preferred embodiment, it is not limited thereto, but can be modified in various manners which are obvious for a person skilled in the art. Thus, it is intended that the present invention is only limited by the scope of the claims attached herewith.
In particular, the present invention is not limited to the material combinations referred to in the above embodiments. Moreover, the invention is applicable for any kind of memory such as DRAM, SRAM, ROM, NVRAM etc.
Patent Application
20080299722
