Stephen S. Pawlowski

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory controller for managing raid information
- Patent number 12,093,566
- Issue date Sep 17, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device protection using interleaved multibit symbols
- Patent number 11,942,175
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Paolo Amato
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended line width memory-side cache systems and methods
- Patent number 11,461,011
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device protection using interleaved multibit symbols
- Patent number 11,404,136
- Issue date Aug 2, 2022
- Micron Technology, Inc.
- Paolo Amato
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive line width cache systems and methods
- Patent number 11,086,526
- Issue date Aug 10, 2021
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended line width memory-side cache systems and methods
- Patent number 10,831,377
- Issue date Nov 10, 2020
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended line width memory-side cache systems and methods
- Patent number 10,691,347
- Issue date Jun 23, 2020
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initialization trace of a computing device
- Patent number 10,146,657
- Issue date Dec 4, 2018
- Intel Corporation
- Robert C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral protocol negotiation
- Patent number 9,547,615
- Issue date Jan 17, 2017
- Intel Corporation
- Dennis M. Bell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Filter micro-coded accelerator
- Patent number 7,831,819
- Issue date Nov 9, 2010
- Intel Corporation
- Anthony L. Chun
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mechanism for efficiently processing deferred order-dependent memor...
- Patent number RE40921
- Issue date Sep 22, 2009
- Intel Corporation
- William S. Wu
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
Bandpass amplifier, method, and system
- Patent number 7,519,344
- Issue date Apr 14, 2009
- Intel Corporation
- Luiz M. Franca-Neto
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
General input/output architecture, protocol and related methods to...
- Patent number 7,231,486
- Issue date Jun 12, 2007
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced highly pipelined bus architecture
- Patent number 6,907,487
- Issue date Jun 14, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop phase in a highly pipelined bus architecture
- Patent number 6,880,031
- Issue date Apr 12, 2005
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,807,592
- Issue date Oct 19, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Response and data phases in a highly pipelined bus architecture
- Patent number 6,804,735
- Issue date Oct 12, 2004
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing deferred transactions
- Patent number RE38388
- Issue date Jan 13, 2004
- Intel Corporation
- Nitin V. Sarangdhar
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,609,171
- Issue date Aug 19, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quad pumped bus architecture and protocol
- Patent number 6,601,121
- Issue date Jul 29, 2003
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-processor system for selecting a processor which has successf...
- Patent number 6,594,756
- Issue date Jul 15, 2003
- Intel Corporation
- Sham Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system including a memory controller having a data strobe ge...
- Patent number 6,557,071
- Issue date Apr 29, 2003
- Intel Corporation
- Patrick F. Stolt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system formed with a processor and a system board provided...
- Patent number 6,487,655
- Issue date Nov 26, 2002
- Intel Corporation
- Frank L. Wildgrube
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and mechanism for virtualizing legacy sideband signals in a...
- Patent number 6,446,154
- Issue date Sep 3, 2002
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and apparatus including lowest priority logic to select a pr...
- Patent number 6,418,496
- Issue date Jul 9, 2002
- Intel Corporation
- Stephen S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for reducing asynchronous service latency in a time slot-...
- Patent number 6,415,367
- Issue date Jul 2, 2002
- Intel Corporation
- Brent S. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for minimizing CPU memory latency while transferring streami...
- Patent number 6,412,049
- Issue date Jun 25, 2002
- Intel Corporation
- Brent S. Baxter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting multiple overlapping address sp...
- Patent number 6,412,060
- Issue date Jun 25, 2002
- Intel Corporation
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data flow control mechanism for a bus supporting two-and three-agen...
- Patent number 6,405,271
- Issue date Jun 11, 2002
- Intel Corporation
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanisms for converting interrupt request signals on address and...
- Patent number 6,401,153
- Issue date Jun 4, 2002
- Intel Corporation
- Stephen S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CONTROLLER FOR MANAGING RAID INFORMATION
- Publication number 20240427526
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER ARCHITECTURE
- Publication number 20240004799
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Emanuele Confalonieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY APPARATUS FOR PROVIDING RELIABILITY, AVAILABILITY, AND SERVI...
- Publication number 20240004807
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Paolo Amato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE BYPASS
- Publication number 20230418756
- Publication date Dec 28, 2023
- Micron Technology, Inc.
- Emanuele Confalonieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER FOR MANAGING RAID INFORMATION
- Publication number 20230280940
- Publication date Sep 7, 2023
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE PROTECTION USING INTERLEAVED MULTIBIT SYMBOLS
- Publication number 20220359034
- Publication date Nov 10, 2022
- Micron Technology, Inc.
- Paolo Amato
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE PROTECTION USING INTERLEAVED MULTIBIT SYMBOLS
- Publication number 20220189574
- Publication date Jun 16, 2022
- Micron Technology, Inc.
- Paolo Amato
- G11 - INFORMATION STORAGE
Information Patent Application
EXTENDED LINE WIDTH MEMORY-SIDE CACHE SYSTEMS AND METHODS
- Publication number 20210048951
- Publication date Feb 18, 2021
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDED LINE WIDTH MEMORY-SIDE CACHE SYSTEMS AND METHODS
- Publication number 20200285400
- Publication date Sep 10, 2020
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE LINE WIDTH CACHE SYSTEMS AND METHODS
- Publication number 20190377500
- Publication date Dec 12, 2019
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDED LINE WIDTH MEMORY-SIDE CACHE SYSTEMS AND METHODS
- Publication number 20190377679
- Publication date Dec 12, 2019
- Micron Technology, Inc.
- Richard C. Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERAL PROTOCOL NEGOTIATION
- Publication number 20160117278
- Publication date Apr 28, 2016
- Dennis M. Bell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INITIALIZATION TRACE OF A COMPUTING DEVICE
- Publication number 20150278068
- Publication date Oct 1, 2015
- Robert C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for communicating within a segmented network
- Publication number 20060104270
- Publication date May 18, 2006
- Inching Chen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Filter micro-coded accelerator
- Publication number 20050219251
- Publication date Oct 6, 2005
- Anthony L. Chun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bandpass amplifier, method, and system
- Publication number 20050218974
- Publication date Oct 6, 2005
- Intel Corporation
- Luiz M. Franca-Neto
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Trigger queue for a filter micro-coded accelerator
- Publication number 20050223380
- Publication date Oct 6, 2005
- Anthony L. Chun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable panel controller and flexible display interface
- Publication number 20030117382
- Publication date Jun 26, 2003
- Stephen S. Pawlowski
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
General input/output architecture, protocol and related methods to...
- Publication number 20030115380
- Publication date Jun 19, 2003
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for supporting multiple overlapping address sp...
- Publication number 20020166039
- Publication date Nov 7, 2002
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Response and data phases in a highly pipelined bus architecture
- Publication number 20020147875
- Publication date Oct 10, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020038397
- Publication date Mar 28, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quad pumped bus architecture and protocol
- Publication number 20020029307
- Publication date Mar 7, 2002
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND APPARATUS INCLUDING LOWEST PRIORITY LOGIC TO SELECT A PR...
- Publication number 20010052043
- Publication date Dec 13, 2001
- STEPHEN S. PAWLOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced highly pipelined bus architecture
- Publication number 20010037421
- Publication date Nov 1, 2001
- Intel Corporation
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop phase in a highly pipelined bus architecture
- Publication number 20010037424
- Publication date Nov 1, 2001
- Gurbir Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISMS FOR CONVERTING INTERRUPT REQUEST SIGNALS ON ADDRESS AND...
- Publication number 20010032284
- Publication date Oct 18, 2001
- STEPHEN S. PAWLOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISMS FOR CONVERTING ADDRESS AND DATA SIGNALS TO INTERRUPT MES...
- Publication number 20010032285
- Publication date Oct 18, 2001
- STEPHEN S. PAWLOWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanisms for converting interrupt request signals on address and...
- Publication number 20010032286
- Publication date Oct 18, 2001
- Stephen S. Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for supporting multiple overlapping address sp...
- Publication number 20010014935
- Publication date Aug 16, 2001
- Peter D. MacWilliams
- G06 - COMPUTING CALCULATING COUNTING

Stephen S. Pawlowski

Person

Patents Grantslast 30 patents

Memory controller for managing raid information

Memory device protection using interleaved multibit symbols

Extended line width memory-side cache systems and methods

Memory device protection using interleaved multibit symbols

Adaptive line width cache systems and methods

Extended line width memory-side cache systems and methods

Extended line width memory-side cache systems and methods

Initialization trace of a computing device

Peripheral protocol negotiation

Filter micro-coded accelerator

Mechanism for efficiently processing deferred order-dependent memor...

Bandpass amplifier, method, and system

General input/output architecture, protocol and related methods to...

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Response and data phases in a highly pipelined bus architecture

Method and apparatus for performing deferred transactions

Quad pumped bus architecture and protocol

Quad pumped bus architecture and protocol

Multi-processor system for selecting a processor which has successf...

Memory system including a memory controller having a data strobe ge...

Computer system formed with a processor and a system board provided...

Method and mechanism for virtualizing legacy sideband signals in a...

System and apparatus including lowest priority logic to select a pr...

Apparatus for reducing asynchronous service latency in a time slot-...

Method for minimizing CPU memory latency while transferring streami...

Method and apparatus for supporting multiple overlapping address sp...

Data flow control mechanism for a bus supporting two-and three-agen...

Mechanisms for converting interrupt request signals on address and...

Patents Applicationslast 30 patents

MEMORY CONTROLLER FOR MANAGING RAID INFORMATION

MEMORY CONTROLLER ARCHITECTURE

MEMORY APPARATUS FOR PROVIDING RELIABILITY, AVAILABILITY, AND SERVI...

CACHE BYPASS

MEMORY CONTROLLER FOR MANAGING RAID INFORMATION

MEMORY DEVICE PROTECTION USING INTERLEAVED MULTIBIT SYMBOLS

MEMORY DEVICE PROTECTION USING INTERLEAVED MULTIBIT SYMBOLS

EXTENDED LINE WIDTH MEMORY-SIDE CACHE SYSTEMS AND METHODS

EXTENDED LINE WIDTH MEMORY-SIDE CACHE SYSTEMS AND METHODS

ADAPTIVE LINE WIDTH CACHE SYSTEMS AND METHODS

EXTENDED LINE WIDTH MEMORY-SIDE CACHE SYSTEMS AND METHODS

PERIPHERAL PROTOCOL NEGOTIATION

INITIALIZATION TRACE OF A COMPUTING DEVICE

Method and apparatus for communicating within a segmented network

Filter micro-coded accelerator

Bandpass amplifier, method, and system

Trigger queue for a filter micro-coded accelerator

Configurable panel controller and flexible display interface

General input/output architecture, protocol and related methods to...

Method and apparatus for supporting multiple overlapping address sp...

Response and data phases in a highly pipelined bus architecture

Quad pumped bus architecture and protocol

Quad pumped bus architecture and protocol

SYSTEM AND APPARATUS INCLUDING LOWEST PRIORITY LOGIC TO SELECT A PR...

Enhanced highly pipelined bus architecture

Snoop phase in a highly pipelined bus architecture

MECHANISMS FOR CONVERTING INTERRUPT REQUEST SIGNALS ON ADDRESS AND...

MECHANISMS FOR CONVERTING ADDRESS AND DATA SIGNALS TO INTERRUPT MES...

Mechanisms for converting interrupt request signals on address and...

Method and apparatus for supporting multiple overlapping address sp...