Stephen S. Poon

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Capped shallow trench isolation and method of formation
- Patent number 6,146,970
- Issue date Nov 14, 2000
- Motorola Inc.
- Keith E. Witek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a fully self-aligned soi mosfet
- Patent number 5,736,435
- Issue date Apr 7, 1998
- Motorola, Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making CMOS device having reduced parasitic capacitance
- Patent number 5,627,097
- Issue date May 6, 1997
- Motorola, Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a MOSFET device having reduced reverse shor...
- Patent number 5,552,332
- Issue date Sep 3, 1996
- Motorola, Inc.
- Hsing-Huang Tseng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a semiconductor device using dual planariza...
- Patent number 5,459,096
- Issue date Oct 17, 1995
- Motorola Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench isolator structure in an integrated circuit
- Patent number 5,436,488
- Issue date Jul 25, 1995
- Motorola Inc.
- Stephen S. Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming trench isolation structure in an integrated circuit
- Patent number 5,387,540
- Issue date Feb 7, 1995
- Motorola Inc.
- Stephen S. Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device having a planar surface
- Patent number 5,328,553
- Issue date Jul 12, 1994
- Motorola Inc.
- Stephen S. Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a ternary boron nitride film and a meth...
- Patent number 5,324,690
- Issue date Jun 28, 1994
- Motorola Inc.
- Avgerinos V. Gelatos
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Trench structure having a germanium silicate region
- Patent number 5,254,873
- Issue date Oct 19, 1993
- Motorola, Inc.
- Stephen S. Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming trench isolation structure with germanium silicat...
- Patent number 5,190,889
- Issue date Mar 2, 1993
- Motorola, Inc.
- Stephen S. Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for polish planarizing a semiconductor substrate by using a...
- Patent number 5,064,683
- Issue date Nov 12, 1991
- Motorola, Inc.
- Stephen S. Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDD transistor process having doping sensitive endpoint etching
- Patent number 4,978,626
- Issue date Dec 18, 1990
- Motorola, Inc.
- Stephen S. Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming layered polysilicon filled contact by doping sens...
- Patent number 4,829,024
- Issue date May 9, 1989
- Motorola, Inc.
- Jeffrey L. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDD CMOS process
- Patent number 4,753,898
- Issue date Jun 28, 1988
- Motorola, Inc.
- Louis C. Parrillo
- H01 - BASIC ELECTRIC ELEMENTS

Stephen S. Poon

Person

Patents Grantslast 30 patents

Capped shallow trench isolation and method of formation

Process for fabricating a fully self-aligned soi mosfet

Method for making CMOS device having reduced parasitic capacitance

Process for fabricating a MOSFET device having reduced reverse shor...

Process for fabricating a semiconductor device using dual planariza...

Trench isolator structure in an integrated circuit

Method of forming trench isolation structure in an integrated circuit

Method for fabricating a semiconductor device having a planar surface

Semiconductor device having a ternary boron nitride film and a meth...

Trench structure having a germanium silicate region

Method of forming trench isolation structure with germanium silicat...

Method for polish planarizing a semiconductor substrate by using a...

LDD transistor process having doping sensitive endpoint etching

Method of forming layered polysilicon filled contact by doping sens...

LDD CMOS process