Steven F. Oakland

Person

Colchester, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit for detecting structural defects in an integrated circuit c...
- Patent number 9,599,664
- Issue date Mar 21, 2017
- GLOBALFOUNDRIES Inc.
- Luke D. Lacroix
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Verifying partial good voltage island structures
- Patent number 9,172,373
- Issue date Oct 27, 2015
- GlobalFoundries U.S. 2 LLC
- Kevin W. Gorman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for detecting structural defects in an integrated circuit c...
- Patent number 9,057,760
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Luke D. Lacroix
- G01 - MEASURING TESTING
Information Patent Grant
Dense register array for enabling scan out observation of both L1 a...
- Patent number 8,423,844
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Grant
Microcontroller for logic built-in self test (LBIST)
- Patent number 8,423,847
- Issue date Apr 16, 2013
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Method to test hold path faults using functional clocking
- Patent number 8,230,283
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Grant
Microcontroller for logic built-in self test (LBIST)
- Patent number 8,205,124
- Issue date Jun 19, 2012
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Hold transition fault model and test generation method
- Patent number 8,181,135
- Issue date May 15, 2012
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,840,864
- Issue date Nov 23, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,840,863
- Issue date Nov 23, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
System and methods of balancing scan chains and inserting the balan...
- Patent number 7,823,035
- Issue date Oct 26, 2010
- International Business Machines Corporation
- David D. Litten
- G01 - MEASURING TESTING
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,698,611
- Issue date Apr 13, 2010
- International Business Machines Corporation
- Gary Grise
- G01 - MEASURING TESTING
Information Patent Grant
Latch and clock structures for enabling race-reduced MUX scan and L...
- Patent number 7,560,964
- Issue date Jul 14, 2009
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Microcontroller for logic built-in self test (LBIST)
- Patent number 7,490,280
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Latch and clock structures for enabling race-reduced mux scan and L...
- Patent number 7,482,851
- Issue date Jan 27, 2009
- International Business Machines Corporation
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Grant
Clock generator having improved deskewer
- Patent number 7,456,674
- Issue date Nov 25, 2008
- International Business Machines Corporation
- Steven F. Oakland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structure for in-system redundant array repair in integrated...
- Patent number 7,457,187
- Issue date Nov 25, 2008
- International Business Machines Corporation
- Arthur A. Bright
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing using independently controllable voltage islands
- Patent number 7,428,675
- Issue date Sep 23, 2008
- International Business Machines Corporation
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for in-system redundant array repair on integr...
- Patent number 7,405,990
- Issue date Jul 29, 2008
- International Business Machines Corporation
- Arthur A. Bright
- G11 - INFORMATION STORAGE
Information Patent Grant
Compilable memory structure and test methodology for both ASIC and...
- Patent number 7,404,125
- Issue date Jul 22, 2008
- International Business Machines Corporation
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for in-system redundant array repair on integr...
- Patent number 7,397,709
- Issue date Jul 8, 2008
- International Business Machines Corporation
- Arthur A. Bright
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for in-system redundant array repair on integr...
- Patent number 7,310,278
- Issue date Dec 18, 2007
- International Business Machines Corporation
- Arthur A. Bright
- G11 - INFORMATION STORAGE
Information Patent Grant
Functional frequency testing of integrated circuits
- Patent number 7,290,191
- Issue date Oct 30, 2007
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Access method for embedded JTAG TAP controller instruction registers
- Patent number 7,284,172
- Issue date Oct 16, 2007
- International Business Machines Corporation
- Richard J. Grupp
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuit using boundary scan cells for design library ana...
- Patent number 7,281,182
- Issue date Oct 9, 2007
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Grant
Method for separating shift and scan paths on scan-only, single por...
- Patent number 7,243,279
- Issue date Jul 10, 2007
- International Business Machines Corporation
- Darren L. Anand
- G01 - MEASURING TESTING
Information Patent Grant
Method for reduced electrical fusing time
- Patent number 7,089,136
- Issue date Aug 8, 2006
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance state saving circuit
- Patent number 6,927,614
- Issue date Aug 9, 2005
- International Business Machines Corporation
- Steven F. Oakland
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pipeline array
- Patent number 6,856,270
- Issue date Feb 15, 2005
- International Business Machines Corporation
- Henry R. Farmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of electrically blowing fuses under control of an on-chip te...
- Patent number 6,768,694
- Issue date Jul 27, 2004
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT C...
- Publication number 20150247896
- Publication date Sep 3, 2015
- International Business Machines Corporation
- Luke D. Lacroix
- G01 - MEASURING TESTING
Information Patent Application
VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES
- Publication number 20150070048
- Publication date Mar 12, 2015
- International Business Machines Corporation
- Kevin W. GORMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
- Publication number 20120221910
- Publication date Aug 30, 2012
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT C...
- Publication number 20120187953
- Publication date Jul 26, 2012
- International Business Machines Corporation
- Luke D. LACROIX
- G01 - MEASURING TESTING
Information Patent Application
DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 A...
- Publication number 20120179944
- Publication date Jul 12, 2012
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Application
METHOD TO TEST HOLD PATH FAULTS USING FUNCTIONAL CLOCKING
- Publication number 20110154141
- Publication date Jun 23, 2011
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Application
Hold Transition Fault Model and Test Generation Method
- Publication number 20110055650
- Publication date Mar 3, 2011
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20100088561
- Publication date Apr 8, 2010
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20100088562
- Publication date Apr 8, 2010
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
- Publication number 20090055696
- Publication date Feb 26, 2009
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHODS OF BALANCING SCAN CHAINS AND INSERTING THE BALAN...
- Publication number 20080288841
- Publication date Nov 20, 2008
- David D. Litten
- G01 - MEASURING TESTING
Information Patent Application
Testing Using Independently Controllable Voltage Islands
- Publication number 20080284459
- Publication date Nov 20, 2008
- International Business Machines Corporation
- Anne E. Gattiker
- G01 - MEASURING TESTING
Information Patent Application
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND...
- Publication number 20080256405
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable Locking Mechanism For Secure Applications In An Integr...
- Publication number 20080155151
- Publication date Jun 26, 2008
- International Business Machines Corporation
- John A. Fifield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK GENERATOR HAVING IMPROVED DESKEWER
- Publication number 20080122515
- Publication date May 29, 2008
- International Business Machines Corporation
- Steven F. Oakland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGR...
- Publication number 20080080274
- Publication date Apr 3, 2008
- International Business Machines Corporation
- Arthur A. Bright
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN STRUCTURE FOR IN-SYSTEM REDUNDANT ARRAY REPAIR IN INTEGRATED...
- Publication number 20080062783
- Publication date Mar 13, 2008
- International Business Machines Corporation
- Arthur A. BRIGHT
- G11 - INFORMATION STORAGE
Information Patent Application
LATCH AND CLOCK STRUCTURES FOR ENABLING RACE-REDUCED MUX SCAN AND L...
- Publication number 20080042712
- Publication date Feb 21, 2008
- International Business Machines Corporation
- David E. LACKEY
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGR...
- Publication number 20080037350
- Publication date Feb 14, 2008
- International Business Machines Corporation
- Arthur A. Bright
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN CHAIN CIRCUITRY THAT ENABLES SCAN TESTING AT FUNCTIONAL CLOCK...
- Publication number 20080005634
- Publication date Jan 3, 2008
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20070283201
- Publication date Dec 6, 2007
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGR...
- Publication number 20070258296
- Publication date Nov 8, 2007
- International Business Machines Corporation
- Arthur A. Bright
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK GENERATOR HAVING IMPROVED DESKEWER
- Publication number 20070200597
- Publication date Aug 30, 2007
- Steven F. Oakland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
- Publication number 20070204193
- Publication date Aug 30, 2007
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTU...
- Publication number 20060248417
- Publication date Nov 2, 2006
- International Business Machines Corporation
- Henry R. Farmer
- G01 - MEASURING TESTING
Information Patent Application
Latch and clock structures for enabling race-reduced MUX scan and L...
- Publication number 20060208783
- Publication date Sep 21, 2006
- IBM Corporation (International Business Machines)
- David E. Lackey
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND CIRCUIT USING BOUNDARY SCAN CELLS FOR DESIGN LIBRARY ANA...
- Publication number 20060190784
- Publication date Aug 24, 2006
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Application
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND...
- Publication number 20060176745
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Application
Testing using independently controllable voltage islands
- Publication number 20060158222
- Publication date Jul 20, 2006
- Anne Gattiker
- G01 - MEASURING TESTING
Information Patent Application
FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS
- Publication number 20060041802
- Publication date Feb 23, 2006
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY

Steven F. Oakland

Person

Patents Grantslast 30 patents

Circuit for detecting structural defects in an integrated circuit c...

Verifying partial good voltage island structures

Circuit for detecting structural defects in an integrated circuit c...

Dense register array for enabling scan out observation of both L1 a...

Microcontroller for logic built-in self test (LBIST)

Method to test hold path faults using functional clocking

Microcontroller for logic built-in self test (LBIST)

Hold transition fault model and test generation method

Functional frequency testing of integrated circuits

Functional frequency testing of integrated circuits

System and methods of balancing scan chains and inserting the balan...

Functional frequency testing of integrated circuits

Latch and clock structures for enabling race-reduced MUX scan and L...

Microcontroller for logic built-in self test (LBIST)

Latch and clock structures for enabling race-reduced mux scan and L...

Clock generator having improved deskewer

Design structure for in-system redundant array repair in integrated...

Testing using independently controllable voltage islands

Method and apparatus for in-system redundant array repair on integr...

Compilable memory structure and test methodology for both ASIC and...

Method and apparatus for in-system redundant array repair on integr...

Method and apparatus for in-system redundant array repair on integr...

Functional frequency testing of integrated circuits

Access method for embedded JTAG TAP controller instruction registers

Method and circuit using boundary scan cells for design library ana...

Method for separating shift and scan paths on scan-only, single por...

Method for reduced electrical fusing time

High performance state saving circuit

Pipeline array

Method of electrically blowing fuses under control of an on-chip te...

Patents Applicationslast 30 patents

CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT C...

VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES

MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)

CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT C...

DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 A...

METHOD TO TEST HOLD PATH FAULTS USING FUNCTIONAL CLOCKING

Hold Transition Fault Model and Test Generation Method

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS

MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)

SYSTEM AND METHODS OF BALANCING SCAN CHAINS AND INSERTING THE BALAN...

Testing Using Independently Controllable Voltage Islands

COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND...

Programmable Locking Mechanism For Secure Applications In An Integr...

CLOCK GENERATOR HAVING IMPROVED DESKEWER

METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGR...

DESIGN STRUCTURE FOR IN-SYSTEM REDUNDANT ARRAY REPAIR IN INTEGRATED...

LATCH AND CLOCK STRUCTURES FOR ENABLING RACE-REDUCED MUX SCAN AND L...

METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGR...

SCAN CHAIN CIRCUITRY THAT ENABLES SCAN TESTING AT FUNCTIONAL CLOCK...

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS

METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGR...

CLOCK GENERATOR HAVING IMPROVED DESKEWER

MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)

CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTU...

Latch and clock structures for enabling race-reduced MUX scan and L...

METHOD AND CIRCUIT USING BOUNDARY SCAN CELLS FOR DESIGN LIBRARY ANA...

COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND...

Testing using independently controllable voltage islands

FUNCTIONAL FREQUENCY TESTING OF INTEGRATED CIRCUITS