BRIEF DESCRIPTION OF THE DRAWINGS
For the purpose of illustrating the invention, the drawings show a form of the invention that is presently preferred. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein:
FIG. 1 is a high-level schematic diagram of an integrated circuit (IC) chip that includes boundary scan circuitry;
FIG. 2 is a schematic diagram of a prior art scan cell suitable for use with the boundary scan circuitry of FIG. 1;
FIG. 3 is a schematic diagram of a scan cell of the present invention that is suitable for use with the boundary scan circuitry of FIG. 1; and
FIG. 4 is a schematic diagram of an alternative scan cell of the present invention that is suitable for use with the boundary scan circuitry of FIG. 1.
DETAILED DESCRIPTION
FIG. 3 shows a scan cell 100 of the present invention that may be used in scan circuitry, such as boundary scan circuitry arrangement 18 of FIG. 1. Scan cell 100 of FIG. 3 is unique in that it allows functional circuitry, e.g., core logic 14 of FIG. 1, located on the same integrated circuit (IC) chip, e.g., IC chip 10, as the scan cell to be transition delay tested at the normal operating functional speed of that circuitry. That is, scan cell 100 is configured to provide transition delay test data comprising one or more “flip-flop” transitions (e.g., 1→0, 0→1, 1→0→1, 0→1→0, etc.) to the functional circuitry at the speed that the circuitry was designed to function at under normal operating conditions, i.e., “functional speed,” so as to test the at-speed integrity of the circuitry. This functional speed is often much faster than a typical scan speed of 50 MHz to 125 MHz and can be in the Gigahertz range.
Scan cell 100 may include a first multiplexer (MUX) 102, a first scan register (e.g., flip-flop or latch) 104, a second scan register (e.g., flip-flop or latch) 108 and a second MUX 112. First multiplexer 102 may have as its selectable inputs a Scan In input 116 and a “Signal In” input 144 and is responsive to a “Shift/Load” selector signal 106. Depending on the location of scan cell 100 within a scan chain, Scan In input 116 may be connected to a test access port (TAP) (not shown, but like TAP 22 of FIG. 1) or the scan chain path output (e.g., either scan chain path output 124A or 124B) of another like scan cell. First scan register 104 is responsive to the output 122 of multiplexer 102 and a “Test Clock” signal 120. Test Clock signal 120 may be generated by suitable test clock circuitry (not shown) that oscillates at a speed lower than the functional speed. For example, if the functional speed of the functional circuitry at issue is on the order of 1 GHz, the speed of Test Clock signal 120 may be on the order of tens of MHz. Of course, as those skilled in the art will readily appreciate, these speeds are simply illustrative and by no means limiting.
Second scan register 108 may be respectively responsive to the output 128 of first scan register 104 and a clock signal 132 output from an OR-gate 136 having Test Clock signal 120 as one of its inputs and a Functional Clock signal 140 as the other of its inputs. Functional Clock signal 140 may be generated by suitable functional clock circuitry (not shown) that oscillates at the functional speed of the functional block at issue. The speed of the functional clock circuitry will typically be on the order of 1 GHz or more. MUX 112 may have as its inputs a Signal In input 144 connected to a signal contact or pin (not shown) and the output 148 of second scan register 108 and may be responsive to a Test signal 152. For example, when Test signal 152 is low, thereby indicating a normal, or non-test mode, MUX 112 would output the signal on Signal In input 144. Correspondingly, when Test signal 152 is high, thereby indicating the test mode, MUX 112 would output output 148 of second scan register 108. When second scan register 108 is clocked by Functional Clock signal 140 and Test signal 152 is high, indicating the test mode, a test data signal 154 having a transition will be output by the second scan register, if during a scan, a different value was loaded into first scan register 104 than was loaded into the second scan register (108) and MUX 112. Due to the at least one flip-flop transition caused by a transition of Functional Clock signal 140, test data signal 154 may be considered a functional speed transition delay test signal.
Depending upon how multiple ones of scan cell 100 are chained together to form a scan chain, e.g., scan chain 26 of FIG. 1, there are generally two scan chain paths 156A-B for cascading test values into the scan chain. If scan chain path output 124A of scan cell 100 is connected to the Scan In input (116) of a downstream like scan cell, the cascading of test values will proceed along scan chain path 156A that essentially cascades test values through only first scan register 104 and bypassing second scan register 108. Alternatively, if scan chain path output 124B is connected to the Scan In input (116) of a downstream like scan cell, the cascading of test values will proceed along scan chain path 156B that cascades test values through both first and second scan registers 104, 108. As those skilled in the art will appreciate, scan chain path 156B has greater flexibility in loading first and second scan registers 104, 108 with the desired test values. During cascading of test values into the scan chain, the functional clock is disabled so that clock signal 132 input into second scan register 108 is the slow speed Test Clock signal 120 that is also input into first scan register 104.
Although not shown, it is noted that scan cell 100 need not include first MUX 102 upstream of the first scan register 104. When provided, MUX 102 allows for loading of scan cell 100 via an external pin (not shown) through Signal In input 144 or via the scan chain through Scan In input 116. Those skilled in the art will readily understand how to modify scan cell 100 of FIG. 3 to exclude MUX 102.
FIG. 4 illustrates another scan cell 200 of the present invention. Scan cell 200 is generally suited for providing test data at functional speed to another chip (not shown) via the output pins of an IC chip, e.g., output pins 204 (FIG. 1) of IC chip 10. This allows scan cell 200 to be used to verify the integrity of the inter-chip circuitry, e.g., connections, at full functional speed using scanning techniques. Like scan cell 100 of FIG. 3, scan cell 200 of FIG. 4 includes first and second scan registers (flip-flops or latches) 208, 212 and a MUX 216. However, instead of MUX 216 having a Signal In input corresponding to Signal In input 144 of FIG. 3, one of the inputs to MUX 216 of FIG. 4 is the output 220 of first scan register 208 and the other of the inputs is the output 224 of second scan register 212. Other aspects of scan cell 200 may be identical to scan cell 100 of FIG. 3. That is, first scan register 208 may be responsive to a Scan In input 228 and a Test Clock signal 232. Depending on the location of scan cell 200 within a scan chain, Scan In input 228 may be connected to a test access port (TAP) (not shown, but like TAP 22 of FIG. 1) or the scan chain path output (e.g., either scan chain path output 236A or 236B) of another like scan cell. Test Clock signal 232 may be generated by suitable test clock circuitry (not shown) that oscillates at a speed lower than the functional speed. For example, if the functional speed of the functional circuitry at issue is on the order of 1 GHz, the speed of Test Clock signal 232 may be on the order of tens of MHz. Of course, as those skilled in the art will readily appreciate, these speeds are simply illustrative and by no means limiting.
Second scan register 212 may be responsive to the output 220 of first scan register 208 and a clock signal 240 output from an OR-gate 244 having Test Clock signal 232 as one of its inputs and a Functional Clock signal 248 as the other of its inputs. Functional Clock signal 248 may be generated by suitable functional clock circuitry (not shown) that oscillates at the functional speed of the functional block at issue. The speed of the functional clock circuitry will typically be on the order of 1 GHz or more. MUX 216 may be responsive to a Test signal 252. For example, when Test signal 252 is low, thereby indicating a normal, or non-test mode, MUX 216 would output the signal present on output 220 of first scan register 208. Correspondingly, when Test signal 252 is high, thereby indicating the test mode, MUX 216 would output the signal present on output 224 of second scan register 212. When second scan register 212 is clocked by Functional Clock signal 248 and Test signal 252 is high, indicating the test mode, a test data signal 254 having a transition will be output by the second scan register, if during scan, a different value was loaded into first scan register 208 than was loaded into second scan register 212 and MUX 216. Due to the at least one flip-flop transition, test data signal 254 may be considered a functional speed transition delay test signal.
Depending upon how multiple ones of scan cell 200 are chained together to form a scan chain, e.g., scan chain 26 of FIG. 1, there are generally two scan chain paths 256A-B for cascading test values into the scan chain. If scan chain path output 236A of scan cell 200 is connected to the Scan In input (228) of a downstream like scan cell, the cascading of test values will proceed along scan chain path 256A that essentially cascades test values through only first scan register 208 and bypassing second scan register 212. Alternatively, if scan chain path output 236B is connected to the Scan In input (228) of a downstream like scan cell, the cascading of test values will proceed along scan chain path 256B that cascades test values through both first and second scan registers 208, 212. As those skilled in the art will appreciate, scan chain path 256B has greater flexibility in loading first and second scan registers 208, 212 with the desired test values. During cascading of test values into the scan chain, the functional clock is disabled so that clock signal 240 input into second scan register 212 is the slow speed Test Clock signal 232 that is also input into first scan register 208.
Although the invention has been described and illustrated with respect to exemplary embodiments thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without parting from the spirit and scope of the present invention.
Patent Application
20080005634
