Steven K. Fong

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Simultaneous development of complementary IC families
- Patent number 8,539,409
- Issue date Sep 17, 2013
- Lattice Semiconductor Corporation
- Shawn Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Step down dechucking
- Patent number 8,164,879
- Issue date Apr 24, 2012
- Advanced Ion Beam Technology, Inc.
- Terry Sheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for monitoring leakage current of a faraday cup
- Patent number 8,040,124
- Issue date Oct 18, 2011
- Advanced Ion Beam Technology, Inc.
- Don Berrian
- G01 - MEASURING TESTING
Information Patent Grant
Shallow trench isolation (STI) with trench liner of increased thick...
- Patent number 7,989,911
- Issue date Aug 2, 2011
- Lattice Semiconductor Corporation
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation (STI) with trench liner of increased thick...
- Patent number 7,985,656
- Issue date Jul 26, 2011
- Lattice Semiconductor Corporation
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complementary avalanche injection EEPROM cell
- Patent number 6,570,212
- Issue date May 27, 2003
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM cell with tunneling across entire separated channels
- Patent number 6,404,006
- Issue date Jun 11, 2002
- Vantis Corporation
- Xiao-Yu Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Avalanche injection EEPROM memory cell with P-type control gate
- Patent number 6,326,663
- Issue date Dec 4, 2001
- Vantis Corporation
- Xiao-Yu Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM cell with tunneling at separate edge and channel regions
- Patent number 6,294,810
- Issue date Sep 25, 2001
- Vantis Corporation
- Xiao-Yu Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Two transistor EEPROM cell
- Patent number 6,294,811
- Issue date Sep 25, 2001
- Vantis Corporation
- Steven J. Fong
- G11 - INFORMATION STORAGE
Information Patent Grant
PMOS avalanche programmed floating gate memory cell structure
- Patent number 6,215,700
- Issue date Apr 10, 2001
- Vantis Corporation
- Steven J. Fong
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating gate memory apparatus and method for selected programming...
- Patent number 6,064,595
- Issue date May 16, 2000
- Vantis Corporation
- Stewart G. Logie
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero-power CMOS non-volatile memory cell having an avalanche inject...
- Patent number 6,028,789
- Issue date Feb 22, 2000
- Vantis Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge stacking on-chip high-voltage generator and method
- Patent number 5,543,668
- Issue date Aug 6, 1996
- Catalyst Semiconductor, Inc.
- Steven K. Fong
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for forming a dielectric filled trench
- Patent number 4,960,727
- Issue date Oct 2, 1990
- Motorola, Inc.
- Robert Mattox
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench isolation process and structure
- Patent number 4,825,277
- Issue date Apr 25, 1989
- Motorola Inc.
- Robert Mattox
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STEP DOWN DECHUCKING
- Publication number 20100254063
- Publication date Oct 7, 2010
- Terry Sheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Monitoring Leakage of a Faraday Cup
- Publication number 20100207601
- Publication date Aug 19, 2010
- Don Berrian
- G01 - MEASURING TESTING
Information Patent Application
Shallow trench isolation (STI) with trench liner of increased thick...
- Publication number 20070267715
- Publication date Nov 22, 2007
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Variable source resistor for flash memory
- Publication number 20070030736
- Publication date Feb 8, 2007
- Fabiano Fontana
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated three-port receptacle and method for connecting hand and...
- Publication number 20070032789
- Publication date Feb 8, 2007
- Wayne J. Gonnering
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Diode structure for word-line protection in a memory circuit
- Publication number 20060145238
- Publication date Jul 6, 2006
- Fabiano Fontana
- G11 - INFORMATION STORAGE
Information Patent Application
Process for fabricating a semiconductor device having an RTCVD layer
- Publication number 20060128162
- Publication date Jun 15, 2006
- Sunil D. Mehta
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
EEPROM CELL WITH TUNNELING ACROSS ENTIRE SEPARATED CHANNELS
- Publication number 20010030343
- Publication date Oct 18, 2001
- XIA0-YU LI
- H01 - BASIC ELECTRIC ELEMENTS

Steven K. Fong

Person

Patents Grantslast 30 patents

Simultaneous development of complementary IC families

Step down dechucking

Method and apparatus for monitoring leakage current of a faraday cup

Shallow trench isolation (STI) with trench liner of increased thick...

Shallow trench isolation (STI) with trench liner of increased thick...

Complementary avalanche injection EEPROM cell

EEPROM cell with tunneling across entire separated channels

Avalanche injection EEPROM memory cell with P-type control gate

EEPROM cell with tunneling at separate edge and channel regions

Two transistor EEPROM cell

PMOS avalanche programmed floating gate memory cell structure

Floating gate memory apparatus and method for selected programming...

Zero-power CMOS non-volatile memory cell having an avalanche inject...

Charge stacking on-chip high-voltage generator and method

Method for forming a dielectric filled trench

Trench isolation process and structure

Patents Applicationslast 30 patents

STEP DOWN DECHUCKING

Method and Apparatus for Monitoring Leakage of a Faraday Cup

Shallow trench isolation (STI) with trench liner of increased thick...

Variable source resistor for flash memory

Integrated three-port receptacle and method for connecting hand and...

Diode structure for word-line protection in a memory circuit

Process for fabricating a semiconductor device having an RTCVD layer

EEPROM CELL WITH TUNNELING ACROSS ENTIRE SEPARATED CHANNELS