Stewart Logie

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory circuit having non-volatile memory cell and methods of using
- Patent number RE48625
- Issue date Jul 6, 2021
- LATTICE SEMICONDUCTOR CORPORATION
- Ronald L. Cline
Information Patent Grant
Memory circuit having non-volatile memory cell and methods of using
- Patent number RE48570
- Issue date May 25, 2021
- Lattice Semiconductor Corporation
- Ronald L. Cline
Information Patent Grant
Memory circuit having non-volatile memory cell and methods of using
- Patent number 9,672,935
- Issue date Jun 6, 2017
- LATTICE SEMICONDUCTOR CORPORATION
- Ronald L Cline
- G11 - INFORMATION STORAGE
Information Patent Grant
Shallow trench isolation (STI) with trench liner of increased thick...
- Patent number 7,989,911
- Issue date Aug 2, 2011
- Lattice Semiconductor Corporation
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation (STI) with trench liner of increased thick...
- Patent number 7,985,656
- Issue date Jul 26, 2011
- Lattice Semiconductor Corporation
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral high-voltage junction device
- Patent number 7,067,883
- Issue date Jun 27, 2006
- Lattice Semiconductor Corporation
- Stewart Logie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge simulation
- Patent number 7,024,646
- Issue date Apr 4, 2006
- Lattice Semiconductor Corporation
- Stewart Logie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
EEPROM device having an isolation-bounded tunnel capacitor and fabr...
- Patent number 6,841,447
- Issue date Jan 11, 2005
- Lattice Semiconductor Corporation
- Stewart Logie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Zero power memory cell with reduced threshold voltage
- Patent number 6,737,702
- Issue date May 18, 2004
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Zero power memory cell with improved data retention
- Patent number 6,660,579
- Issue date Dec 9, 2003
- Lattice Semiconductor Corp.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact single-poly two transistor EEPROM cell
- Patent number 6,627,947
- Issue date Sep 30, 2003
- Lattice Semiconductor Corporation
- Yongzhong Hu
- G11 - INFORMATION STORAGE
Information Patent Grant
Complementary avalanche injection EEPROM cell
- Patent number 6,570,212
- Issue date May 27, 2003
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for providing electrical insulation for local int...
- Patent number 6,303,949
- Issue date Oct 16, 2001
- Advanced Micro Devices, Inc.
- William George En
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Avalanche programmed floating gate memory cell structure with progr...
- Patent number 6,294,809
- Issue date Sep 25, 2001
- Vantis Corporation
- Stewart G. Logie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PMOS avalanche programmed floating gate memory cell structure
- Patent number 6,215,700
- Issue date Apr 10, 2001
- Vantis Corporation
- Steven J. Fong
- G11 - INFORMATION STORAGE
Information Patent Grant
Floating gate memory apparatus and method for selected programming...
- Patent number 6,064,595
- Issue date May 16, 2000
- Vantis Corporation
- Stewart G. Logie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for providing electrical insulation for local int...
- Patent number 5,956,610
- Issue date Sep 21, 1999
- Advanced Micro Devices, Inc.
- William George En
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory cells using only positive charge to store data
- Patent number 5,742,542
- Issue date Apr 21, 1998
- Advanced Micro Devices, Inc.
- Jonathan Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM using a merged source and control gate
- Patent number 4,924,278
- Issue date May 8, 1990
- Advanced Micro Devices, Inc.
- Stewart Logie
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING
- Publication number 20160111168
- Publication date Apr 21, 2016
- Lattice Semiconductor Corporation
- Ronald L. Cline
- G11 - INFORMATION STORAGE
Information Patent Application
Shallow trench isolation (STI) with trench liner of increased thick...
- Publication number 20070267715
- Publication date Nov 22, 2007
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polycide fuse with reduced programming time
- Publication number 20070111403
- Publication date May 17, 2007
- Chun Jiang
- G11 - INFORMATION STORAGE
Information Patent Application
Electrostatic discharge simulation
- Publication number 20050172246
- Publication date Aug 4, 2005
- Stewart Logie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Lateral high-voltage junction device
- Publication number 20050093069
- Publication date May 5, 2005
- Lattice Semiconductor Corporation
- Stewart Logie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM FOR PROVIDING ELECTRICAL INSULATION FOR LOCAL INT...
- Publication number 20010014527
- Publication date Aug 16, 2001
- WILLIAM GEORGE EN
- H01 - BASIC ELECTRIC ELEMENTS

Stewart Logie

Person

Patents Grantslast 30 patents

Memory circuit having non-volatile memory cell and methods of using

Memory circuit having non-volatile memory cell and methods of using

Memory circuit having non-volatile memory cell and methods of using

Shallow trench isolation (STI) with trench liner of increased thick...

Shallow trench isolation (STI) with trench liner of increased thick...

Lateral high-voltage junction device

Electrostatic discharge simulation

EEPROM device having an isolation-bounded tunnel capacitor and fabr...

Zero power memory cell with reduced threshold voltage

Zero power memory cell with improved data retention

Compact single-poly two transistor EEPROM cell

Complementary avalanche injection EEPROM cell

Method and system for providing electrical insulation for local int...

Avalanche programmed floating gate memory cell structure with progr...

PMOS avalanche programmed floating gate memory cell structure

Floating gate memory apparatus and method for selected programming...

Method and system for providing electrical insulation for local int...

Non-volatile memory cells using only positive charge to store data

EEPROM using a merged source and control gate

Patents Applicationslast 30 patents

MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING

Shallow trench isolation (STI) with trench liner of increased thick...

Polycide fuse with reduced programming time

Electrostatic discharge simulation

Lateral high-voltage junction device

METHOD AND SYSTEM FOR PROVIDING ELECTRICAL INSULATION FOR LOCAL INT...