Subramaniam Maiyuran

Person

Gold River, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction prefetch mechanism
- Patent number 12,164,430
- Issue date Dec 10, 2024
- Intel Corporation
- Vasileios Porpodas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tanh and sigmoid function execution
- Patent number 12,164,884
- Issue date Dec 10, 2024
- Intel Corporation
- Shuai Mu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for error detection and control for embedded me...
- Patent number 12,147,302
- Issue date Nov 19, 2024
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page faulting and selective preemption
- Patent number 12,131,402
- Issue date Oct 29, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,124,383
- Issue date Oct 22, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 12,117,962
- Issue date Oct 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting barycentric planes to attribute planes
- Patent number 12,100,103
- Issue date Sep 24, 2024
- Intel Corporation
- Eric Hoekstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing efficient cross channel operations in parallel computing...
- Patent number 12,093,213
- Issue date Sep 17, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page faulting and selective preemption
- Patent number 12,067,641
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Native support for execution of get exponent, get mantisssa, and sc...
- Patent number 12,067,394
- Issue date Aug 20, 2024
- Intel Corporation
- Shuai Mu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional adjustment of render rate
- Patent number 12,061,831
- Issue date Aug 13, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,056,059
- Issue date Aug 6, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 12,039,001
- Issue date Jul 16, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix multiplication acceleration mechanism
- Patent number 12,008,067
- Issue date Jun 11, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 12,007,935
- Issue date Jun 11, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management for detecting cross tile access provid...
- Patent number 11,995,029
- Issue date May 28, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing structured sparsity in systolic arrays
- Patent number 11,977,885
- Issue date May 7, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 11,954,063
- Issue date Apr 9, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory reconfiguration
- Patent number 11,954,062
- Issue date Apr 9, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assistance for hardware prefetch in cache access
- Patent number 11,934,342
- Issue date Mar 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to perform single precision floating point extended math...
- Patent number 11,934,797
- Issue date Mar 19, 2024
- Intel Corporation
- Abhishek Rhisheekesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute optimization mechanism for deep neural networks
- Patent number 11,922,535
- Issue date Mar 5, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler assisted register file write reduction
- Patent number 11,900,502
- Issue date Feb 13, 2024
- Intel Corporation
- Chandra S. Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tile sequencing mechanism
- Patent number 11,900,539
- Issue date Feb 13, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods to skip inconsequential matrix operations
- Patent number 11,900,114
- Issue date Feb 13, 2024
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 11,892,950
- Issue date Feb 6, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for exploiting queues and transitional storage...
- Patent number 11,869,113
- Issue date Jan 9, 2024
- Intel Corporation
- Aravindh Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory prefetching in multiple GPU environment
- Patent number 11,861,759
- Issue date Jan 2, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...
- Publication number 20240403044
- Publication date Dec 5, 2024
- Intel Corporation
- Shuai MU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20240354043
- Publication date Oct 24, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20240320000
- Publication date Sep 26, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...
- Publication number 20240256274
- Publication date Aug 1, 2024
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20240256456
- Publication date Aug 1, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
- Publication number 20240257294
- Publication date Aug 1, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO PERFORM SINGLE PRECISION FLOATING POINT EXTENDED MATH...
- Publication number 20240241693
- Publication date Jul 18, 2024
- Intel Corporation
- Abhishek Rhisheekesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20240184739
- Publication date Jun 6, 2024
- Intel Corporation
- Joydeep RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE SEQUENCING MECHANISM
- Publication number 20240185527
- Publication date Jun 6, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE...
- Publication number 20240169466
- Publication date May 23, 2024
- Intel Corporation
- Aravindh Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES I...
- Publication number 20240168764
- Publication date May 23, 2024
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT
- Publication number 20240161226
- Publication date May 16, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20240161227
- Publication date May 16, 2024
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES
- Publication number 20240103910
- Publication date Mar 28, 2024
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PREFETCH MECHANISM
- Publication number 20240086329
- Publication date Mar 14, 2024
- Intel Corporation
- Vasileios Porpodas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...
- Publication number 20240086357
- Publication date Mar 14, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Regional Adjustment of Render Rate
- Publication number 20240086138
- Publication date Mar 14, 2024
- Intel Corporation
- Eric J. Asperheim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS
- Publication number 20240078630
- Publication date Mar 7, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS
- Publication number 20240061700
- Publication date Feb 22, 2024
- Intel Corporation
- Rajesh SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES
- Publication number 20240053985
- Publication date Feb 15, 2024
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20240045830
- Publication date Feb 8, 2024
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE
- Publication number 20240004833
- Publication date Jan 4, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS
- Publication number 20240004713
- Publication date Jan 4, 2024
- Intel Corporation
- Abhishek R Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS
- Publication number 20230418617
- Publication date Dec 28, 2023
- Intel Corporation
- Christopher J. HUGHES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARITHMETIC ON SPARSE DATA
- Publication number 20230377209
- Publication date Nov 23, 2023
- Intel Corporation
- ABHISHEK R. APPU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...
- Publication number 20230367740
- Publication date Nov 16, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20230351543
- Publication date Nov 2, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING

Subramaniam Maiyuran

Person

Patents Grantslast 30 patents

Instruction prefetch mechanism

Tanh and sigmoid function execution

Systems and methods for error detection and control for embedded me...

Page faulting and selective preemption

Systems and methods for cache optimization

Scalar core integration

Converting barycentric planes to attribute planes

Compression techniques

Computing efficient cross channel operations in parallel computing...

Page faulting and selective preemption

Cache structure and utilization

Native support for execution of get exponent, get mantisssa, and sc...

Regional adjustment of render rate

Systems and methods for cache optimization

Scalable sparse matrix multiply acceleration using systolic arrays...

Sparse matrix multiplication acceleration mechanism

Graphics processors and graphics processing units having dot produc...

Multi-tile memory management for detecting cross tile access provid...

Utilizing structured sparsity in systolic arrays

Graphics processors and graphics processing units having dot produc...

Dynamic memory reconfiguration

Assistance for hardware prefetch in cache access

Mechanism to perform single precision floating point extended math...

Compute optimization mechanism for deep neural networks

Compiler assisted register file write reduction

Tile sequencing mechanism

Systems and methods to skip inconsequential matrix operations

Data prefetching for graphics data processing

Systems and methods for exploiting queues and transitional storage...

Memory prefetching in multiple GPU environment

Patents Applicationslast 30 patents

NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

Regional Adjustment of Render Rate

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS

MECHANISM TO PERFORM SINGLE PRECISION FLOATING POINT EXTENDED MATH...

DYNAMIC MEMORY RECONFIGURATION

TILE SEQUENCING MECHANISM

SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE...

SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES I...

MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES

INSTRUCTION PREFETCH MECHANISM

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...

Regional Adjustment of Render Rate

GRAPHICS PROCESSING UNIT PROCESSING AND CACHING IMPROVEMENTS

VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS

SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES

SCALAR CORE INTEGRATION

ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE

HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS

DATA LOCALITY ENHANCEMENT FOR GRAPHICS PROCESSING UNITS

SYSTOLIC ARITHMETIC ON SPARSE DATA

COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE