Sukeshwar KANNAN

Person

Malta, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Testing monolithic three dimensional integrated circuits
- Patent number 10,775,429
- Issue date Sep 15, 2020
- Marvell Asia Pte., Ltd.
- Sukeshwar Kannan
- G01 - MEASURING TESTING
Information Patent Grant
Methods of manufacturing RF filters
- Patent number 10,636,776
- Issue date Apr 28, 2020
- GLOBALFOUNDRIES Inc.
- Md. Sayed Kaysar Bin Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and structures for mitigating ESD during wafer bonding
- Patent number 10,236,263
- Issue date Mar 19, 2019
- GLOBALFOUNDRIES Inc.
- Luke England
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep trench metal-insulator-metal capacitors
- Patent number 10,083,958
- Issue date Sep 25, 2018
- GLOBALFOUNDRIES Inc.
- Sukeshwar Kannan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system for voltage compensation in a semicond...
- Patent number 10,069,490
- Issue date Sep 4, 2018
- GLOBALFOUNDRIES Inc.
- Sukeshwar Kannan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Latency compensation network using timing slack sensors
- Patent number 9,716,487
- Issue date Jul 25, 2017
- GLOBALFOUNDRIES Inc.
- Sukeshwar Kannan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DFT structure for TSVs in 3D ICs while maintaining functional purpose
- Patent number 9,460,975
- Issue date Oct 4, 2016
- GLOBALFOUNDRIES Inc.
- Sukeshwar Kannan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
TSV redundancy scheme and architecture using decoder/encoder
- Patent number 9,401,312
- Issue date Jul 26, 2016
- GLOBALFOUNDRIES Inc.
- Sukeshwar Kannan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHODS OF MANUFACTURING RF FILTERS
- Publication number 20190267361
- Publication date Aug 29, 2019
- GLOBALFOUNDRIES INC.
- Md. Sayed Kaysar Bin Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS
- Publication number 20190094294
- Publication date Mar 28, 2019
- DUKE UNIVERSITY
- Sukeshwar Kannan
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING
- Publication number 20190067217
- Publication date Feb 28, 2019
- GLOBALFOUNDRIES INC.
- Luke England
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEP TRENCH METAL-INSULATOR-METAL CAPACITORS
- Publication number 20180108651
- Publication date Apr 19, 2018
- GLOBALFOUNDRIES INC.
- Sukeshwar Kannan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR VOLTAGE COMPENSATION IN A SEMICOND...
- Publication number 20170222634
- Publication date Aug 3, 2017
- GLOBALFOUNDRIES INC.
- Sukeshwar Kannan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR DETECTION OF FAILURES IN UNDER-FILL LAYERS...
- Publication number 20160322265
- Publication date Nov 3, 2016
- GLOBALFOUNDRIES Inc.
- Shan GAO
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATION STRUCTURES FOR HIGH CURRENT APPLICATIONS
- Publication number 20160293579
- Publication date Oct 6, 2016
- GLOBALFOUNDRIES INC.
- Luke ENGLAND
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DFT STRUCTURE FOR TSVS IN 3D ICS WHILE MAINTAINING FUNCTIONAL PURPOSE
- Publication number 20160225679
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Sukeshwar KANNAN
- H01 - BASIC ELECTRIC ELEMENTS

Sukeshwar KANNAN

Person

Patents Grantslast 30 patents

Testing monolithic three dimensional integrated circuits

Methods of manufacturing RF filters

Methods and structures for mitigating ESD during wafer bonding

Deep trench metal-insulator-metal capacitors

Method, apparatus and system for voltage compensation in a semicond...

Latency compensation network using timing slack sensors

DFT structure for TSVs in 3D ICs while maintaining functional purpose

TSV redundancy scheme and architecture using decoder/encoder

Patents Applicationslast 30 patents

METHODS OF MANUFACTURING RF FILTERS

TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS

METHODS AND STRUCTURES FOR MITIGATING ESD DURING WAFER BONDING

DEEP TRENCH METAL-INSULATOR-METAL CAPACITORS

METHOD, APPARATUS AND SYSTEM FOR VOLTAGE COMPENSATION IN A SEMICOND...

METHOD AND APPARATUS FOR DETECTION OF FAILURES IN UNDER-FILL LAYERS...

INTEGRATION STRUCTURES FOR HIGH CURRENT APPLICATIONS

DFT STRUCTURE FOR TSVS IN 3D ICS WHILE MAINTAINING FUNCTIONAL PURPOSE