Suketu Parikh

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low resistance and high reliability metallization module
- Patent number 12,148,660
- Issue date Nov 19, 2024
- Applied Materials, Inc.
- Roey Shaviv
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of modifying portions of layer stacks
- Patent number 12,142,487
- Issue date Nov 12, 2024
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for forming dual metal interconnects
- Patent number 11,948,885
- Issue date Apr 2, 2024
- Applied Materials, Inc.
- Suketu A Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-alignment etching of interconnect layers
- Patent number 11,749,561
- Issue date Sep 5, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistor device
- Patent number 11,682,668
- Issue date Jun 20, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of modifying portions of layer stacks
- Patent number 11,658,041
- Issue date May 23, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-alignment etching of interconnect layers
- Patent number 11,557,509
- Issue date Jan 17, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Film stack for lithography applications
- Patent number 11,495,461
- Issue date Nov 8, 2022
- Applied Materials, Inc.
- Tejinder Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated CMOS source drain formation with advanced control
- Patent number 11,309,404
- Issue date Apr 19, 2022
- Applied Materials, Inc.
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming self-aligned via
- Patent number 11,270,914
- Issue date Mar 8, 2022
- Applied Materials Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistor device
- Patent number 11,177,254
- Issue date Nov 16, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Atomic layer self aligned substrate processing and integrated toolset
- Patent number 11,131,022
- Issue date Sep 28, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Methods and apparatus for forming dual metal interconnects
- Patent number 11,075,165
- Issue date Jul 27, 2021
- Applied Materials, Inc.
- Suketu A Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for cost-effective conversion of unsupervised fault detec...
- Patent number 11,054,815
- Issue date Jul 6, 2021
- Applied Materials, Inc.
- Bradley D. Schulze
- G05 - CONTROLLING REGULATING
Information Patent Grant
Methods and apparatus for fabrication of self aligning interconnect...
- Patent number 11,049,770
- Issue date Jun 29, 2021
- Applied Materials, Inc.
- Suketu A. Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming self-aligned via
- Patent number 10,923,396
- Issue date Feb 16, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for improved performance in semiconductor proce...
- Patent number 10,892,198
- Issue date Jan 12, 2021
- Applied Materials, Inc.
- Chirantha P. Rodrigo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simultaneous metal patterning for 3D interconnects
- Patent number 10,867,858
- Issue date Dec 15, 2020
- Applied Materials, Inc.
- Suketu A. Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Equipment cleaning apparatus and method
- Patent number 10,695,804
- Issue date Jun 30, 2020
- Applied Materials, Inc.
- Roman M. Mostovoy
- B08 - CLEANING
Information Patent Grant
Method of forming self-aligned via
- Patent number 10,629,484
- Issue date Apr 21, 2020
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming an interconnect pattern on a substrate
- Patent number 9,437,479
- Issue date Sep 6, 2016
- Applied Materials, Inc.
- Suketu A. Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact and interconnect metallization for solar cells
- Patent number 9,184,333
- Issue date Nov 10, 2015
- Applied Materials, Inc.
- Suketu Arun Parikh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Integrated three-dimensional and planar metallization structure for...
- Patent number 9,099,584
- Issue date Aug 4, 2015
- Solexel, Inc.
- Suketu Parikh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Structure and method for creating a reusable template for detachabl...
- Patent number 9,053,957
- Issue date Jun 9, 2015
- Solexel, Inc.
- Suketu Parikh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Factory level process and final product performance control system
- Patent number 8,849,438
- Issue date Sep 30, 2014
- Applied Materials, Inc.
- Suketu Arun Parikh
- G05 - CONTROLLING REGULATING
Information Patent Grant
Structure and method for improving solar cell efficiency and mechan...
- Patent number 8,828,517
- Issue date Sep 9, 2014
- Solexel, Inc.
- David Xuan-Qi Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Self aligned narrow storage elements for advanced memory device
- Patent number 8,476,695
- Issue date Jul 2, 2013
- Spansion LLC
- Suketu Arun Parikh
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of creating reusable template for detachable thin film subst...
- Patent number 8,445,314
- Issue date May 21, 2013
- Solexel, Inc.
- Suketu Parikh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method of forming an electronic device including forming a charge s...
- Patent number 8,409,952
- Issue date Apr 2, 2013
- Spansion LLC
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper wiring module control
- Patent number 8,005,634
- Issue date Aug 23, 2011
- Applied Materials, Inc.
- Arulkumar Shanmugasundram
- B24 - GRINDING POLISHING

Patents Applicationslast 30 patents

Information Patent Application
Three-Dimensional Vertical Interconnect Architecture and Methods Fo...
- Publication number 20240387458
- Publication date Nov 21, 2024
- Applied Materials, Inc.
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS
- Publication number 20230360965
- Publication date Nov 9, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE POWER RAIL TO DEEP VIAS
- Publication number 20230068312
- Publication date Mar 2, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED WIDE BACKSIDE POWER RAIL CONTACTS TO MULTIPLE TRANSIST...
- Publication number 20230064183
- Publication date Mar 2, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ULTRA THINNING OF WAFER
- Publication number 20230061392
- Publication date Mar 2, 2023
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR REMOVING ETCH STOP LAYERS
- Publication number 20230035288
- Publication date Feb 2, 2023
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS FOR REMOVING ETCH STOP LAYERS
- Publication number 20230031381
- Publication date Feb 2, 2023
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR SELECTIVE ETCH STOP CAPPING AND SELECTIVE...
- Publication number 20230010568
- Publication date Jan 12, 2023
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURES WITH COPPER DOPED HYBRID METALLIZATION FOR LINE AND VIA
- Publication number 20230005844
- Publication date Jan 5, 2023
- Applied Materials, Inc.
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR COPPER DOPED HYBRID METALLIZATION FOR LINE AND VIA
- Publication number 20230005789
- Publication date Jan 5, 2023
- Suketu PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated CMOS Source Drain Formation With Advanced Control
- Publication number 20220199804
- Publication date Jun 23, 2022
- Applied Materials, Inc.
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI COLOR STACK FOR SELF ALIGNED DUAL PATTERN FORMATION FOR MULTI...
- Publication number 20220130722
- Publication date Apr 28, 2022
- Applied Materials, Inc.
- Suketu Arun PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW RESISTANCE AND HIGH RELIABILITY METALLIZATION MODULE
- Publication number 20220108917
- Publication date Apr 7, 2022
- Applied Materials, Inc.
- Roey Shaviv
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Transistor Device
- Publication number 20220068917
- Publication date Mar 3, 2022
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ATOMIC LAYER SELF ALIGNED SUBSTRATE PROCESSING AND INTEGRATED TOOLSET
- Publication number 20210404061
- Publication date Dec 30, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Atomic Layer Self Aligned Substrate Processing and Integrated Toolset
- Publication number 20210404062
- Publication date Dec 30, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MODIFYING PORTIONS OF LAYER STACKS
- Publication number 20210375636
- Publication date Dec 2, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MODIFYING PORTIONS OF LAYER STACKS
- Publication number 20210375637
- Publication date Dec 2, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR FORMING DUAL METAL INTERCONNECTS
- Publication number 20210320064
- Publication date Oct 14, 2021
- Applied Materials, Inc.
- SUKETU A. PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS
- Publication number 20210305087
- Publication date Sep 30, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method Of Forming Self-Aligned Via
- Publication number 20210166973
- Publication date Jun 3, 2021
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR FORMING DUAL METAL INTERCONNECTS
- Publication number 20210020569
- Publication date Jan 21, 2021
- Applied Materials, Inc.
- SUKETU A. PARIKH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR FABRICATION OF SELF-ALIGNING INTERCONNECT...
- Publication number 20200303254
- Publication date Sep 24, 2020
- Applied Materials, Inc.
- Suketu A. Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FILM STACK FOR LITHOGRAPHY APPLICATIONS
- Publication number 20200273705
- Publication date Aug 27, 2020
- Applied Materials, Inc.
- Tejinder SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method Of Forming Self-Aligned Via
- Publication number 20200219768
- Publication date Jul 9, 2020
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method Of Forming Self-Aligned Via
- Publication number 20200144117
- Publication date May 7, 2020
- Applied Materials, Inc.
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacked Transistor Device
- Publication number 20200118996
- Publication date Apr 16, 2020
- Suketu Arun Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVED PERFORMANCE IN SEMICONDUCTOR PROCE...
- Publication number 20200091018
- Publication date Mar 19, 2020
- Applied Materials, Inc.
- Chirantha P. Rodrigo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIMULTANEOUS METAL PATTERNING FOR 3D INTERCONNECTS
- Publication number 20200091002
- Publication date Mar 19, 2020
- Applied Materials, Inc.
- Suketu A. Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated CMOS Source Drain Formation With Advanced Control
- Publication number 20200013878
- Publication date Jan 9, 2020
- Applied Materials, Inc.
- Benjamin Colombeau
- H01 - BASIC ELECTRIC ELEMENTS

Suketu Parikh

Person

Patents Grantslast 30 patents

Low resistance and high reliability metallization module

Methods of modifying portions of layer stacks

Methods and apparatus for forming dual metal interconnects

Self-alignment etching of interconnect layers

Stacked transistor device

Methods of modifying portions of layer stacks

Self-alignment etching of interconnect layers

Film stack for lithography applications

Integrated CMOS source drain formation with advanced control

Method of forming self-aligned via

Stacked transistor device

Atomic layer self aligned substrate processing and integrated toolset

Methods and apparatus for forming dual metal interconnects

Apparatus for cost-effective conversion of unsupervised fault detec...

Methods and apparatus for fabrication of self aligning interconnect...

Method of forming self-aligned via

Systems and methods for improved performance in semiconductor proce...

Simultaneous metal patterning for 3D interconnects

Equipment cleaning apparatus and method

Method of forming self-aligned via

Methods for forming an interconnect pattern on a substrate

Contact and interconnect metallization for solar cells

Integrated three-dimensional and planar metallization structure for...

Structure and method for creating a reusable template for detachabl...

Factory level process and final product performance control system

Structure and method for improving solar cell efficiency and mechan...

Self aligned narrow storage elements for advanced memory device

Method of creating reusable template for detachable thin film subst...

Method of forming an electronic device including forming a charge s...

Copper wiring module control

Patents Applicationslast 30 patents

Three-Dimensional Vertical Interconnect Architecture and Methods Fo...

SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS

BACKSIDE POWER RAIL TO DEEP VIAS

SELF-ALIGNED WIDE BACKSIDE POWER RAIL CONTACTS TO MULTIPLE TRANSIST...

METHOD OF ULTRA THINNING OF WAFER

METHODS FOR REMOVING ETCH STOP LAYERS

APPARATUS FOR REMOVING ETCH STOP LAYERS

METHODS AND APPARATUS FOR SELECTIVE ETCH STOP CAPPING AND SELECTIVE...

STRUCTURES WITH COPPER DOPED HYBRID METALLIZATION FOR LINE AND VIA

METHODS FOR COPPER DOPED HYBRID METALLIZATION FOR LINE AND VIA

Integrated CMOS Source Drain Formation With Advanced Control

MULTI COLOR STACK FOR SELF ALIGNED DUAL PATTERN FORMATION FOR MULTI...

LOW RESISTANCE AND HIGH RELIABILITY METALLIZATION MODULE

Stacked Transistor Device

ATOMIC LAYER SELF ALIGNED SUBSTRATE PROCESSING AND INTEGRATED TOOLSET

Atomic Layer Self Aligned Substrate Processing and Integrated Toolset

METHODS OF MODIFYING PORTIONS OF LAYER STACKS

METHODS OF MODIFYING PORTIONS OF LAYER STACKS

METHODS AND APPARATUS FOR FORMING DUAL METAL INTERCONNECTS

SELF-ALIGNMENT ETCHING OF INTERCONNECT LAYERS

Method Of Forming Self-Aligned Via

METHODS AND APPARATUS FOR FORMING DUAL METAL INTERCONNECTS

METHODS AND APPARATUS FOR FABRICATION OF SELF-ALIGNING INTERCONNECT...

FILM STACK FOR LITHOGRAPHY APPLICATIONS

Method Of Forming Self-Aligned Via

Method Of Forming Self-Aligned Via

Stacked Transistor Device

SYSTEMS AND METHODS FOR IMPROVED PERFORMANCE IN SEMICONDUCTOR PROCE...

SIMULTANEOUS METAL PATTERNING FOR 3D INTERCONNECTS

Integrated CMOS Source Drain Formation With Advanced Control