Sundar S. Chetlur

Person

Kissmmee, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
MOS transistor and method of manufacture
- Patent number 7,151,059
- Issue date Dec 19, 2006
- Agere Systems Inc.
- Samir Chaudhry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for oxide fabrication using oxidation steps below and above...
- Patent number 7,148,153
- Issue date Dec 12, 2006
- Agere Systems Inc.
- Yuanning Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device free of LLD regions
- Patent number 6,740,912
- Issue date May 25, 2004
- Agere Systems Inc.
- Samir Chaudhry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deuterium passivated semiconductor device having enhanced immunity...
- Patent number 6,674,151
- Issue date Jan 6, 2004
- Agere Systems Inc.
- Sundar S. Chetlur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming semiconductor device with LDD structure
- Patent number 6,576,521
- Issue date Jun 10, 2003
- Agere Systems Inc.
- Samir Chaudhry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREI...
- Patent number 6,551,946
- Issue date Apr 22, 2003
- Agere Systems Inc.
- Yuanning Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing fluid, polishing method, semiconductor device and semicon...
- Patent number 6,439,972
- Issue date Aug 27, 2002
- Agere Systems Guardian Corp.
- Sudhanshu Misra
- B24 - GRINDING POLISHING
Information Patent Grant
Method of determining a trap density of a semiconductor/oxide inter...
- Patent number 6,391,668
- Issue date May 21, 2002
- Agere Systems Guardian Corp.
- Carlos M. Chacon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polishing fluid, polishing method, semiconductor device and semicon...
- Patent number 6,328,633
- Issue date Dec 11, 2001
- Agere Systems Guardian Corp.
- Sudhanshu Misra
- B24 - GRINDING POLISHING
Information Patent Grant
Integrated circuit capacitor including anchored plugs
- Patent number 6,291,848
- Issue date Sep 18, 2001
- Agere Systems Guardian Corp.
- Sundar Srinivasan Chetlur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit capacitor including tapered plug
- Patent number 6,249,016
- Issue date Jun 19, 2001
- Agere Systems Guardian Corp.
- Samir Chaudhry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a getter layer to improve metal to metal contact resistance...
- Patent number 6,228,748
- Issue date May 8, 2001
- Lucent Technologies Inc.
- Steven M. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making integrated circuit capacitor including tapered plug
- Patent number 6,204,186
- Issue date Mar 20, 2001
- Lucent Technologies Inc.
- Samir Chaudhry
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for determining the hot carrier lifetime of a transistor
- Patent number 6,198,301
- Issue date Mar 6, 2001
- Lucent Technologies Inc.
- Sundar Chetlur
- G01 - MEASURING TESTING
Information Patent Grant
Process for deuterium passivation and hot carrier immunity
- Patent number 6,187,665
- Issue date Feb 13, 2001
- Lucent Technologies, Inc.
- Sundar S. Chetlur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making integrated circuit capacitor including anchored p...
- Patent number 6,103,586
- Issue date Aug 15, 2000
- Lucent Technologies Inc.
- Sundar Srinivasan Chetlur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using getter layer to improve metal to metal contact resi...
- Patent number 5,989,984
- Issue date Nov 23, 1999
- Lucent Technologies, Inc.
- Steven M. Anderson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MOS transistor and method of manufacture
- Publication number 20040150014
- Publication date Aug 5, 2004
- Samir Chaudhry
- C30 - CRYSTAL GROWTH
Information Patent Application
Process for oxide fabrication using oxidation steps below and above...
- Publication number 20030143863
- Publication date Jul 31, 2003
- Agere Systems Inc.
- Yuanning Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for oxide fabrication using oxidation steps below and above...
- Publication number 20030119337
- Publication date Jun 26, 2003
- Agere Systems Inc.
- Yuanning Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polishing fluid, polishing method, semiconductor device and semicon...
- Publication number 20010036796
- Publication date Nov 1, 2001
- Lucent Technologies, Inc.
- Sudhanshu Misra
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...

Sundar S. Chetlur

Person

Patents Grantslast 30 patents

MOS transistor and method of manufacture

Process for oxide fabrication using oxidation steps below and above...

Semiconductor device free of LLD regions

Deuterium passivated semiconductor device having enhanced immunity...

Method of forming semiconductor device with LDD structure

TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREI...

Polishing fluid, polishing method, semiconductor device and semicon...

Method of determining a trap density of a semiconductor/oxide inter...

Polishing fluid, polishing method, semiconductor device and semicon...

Integrated circuit capacitor including anchored plugs

Integrated circuit capacitor including tapered plug

Use of a getter layer to improve metal to metal contact resistance...

Method of making integrated circuit capacitor including tapered plug

Method for determining the hot carrier lifetime of a transistor

Process for deuterium passivation and hot carrier immunity

Method for making integrated circuit capacitor including anchored p...

Method of using getter layer to improve metal to metal contact resi...

Patents Applicationslast 30 patents

MOS transistor and method of manufacture

Process for oxide fabrication using oxidation steps below and above...

Process for oxide fabrication using oxidation steps below and above...

Polishing fluid, polishing method, semiconductor device and semicon...