Sunil D. Mehta

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shallow trench isolation (STI) with trench liner of increased thick...
- Patent number 7,989,911
- Issue date Aug 2, 2011
- Lattice Semiconductor Corporation
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation (STI) with trench liner of increased thick...
- Patent number 7,985,656
- Issue date Jul 26, 2011
- Lattice Semiconductor Corporation
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of high voltage transistor with high breakdown voltage
- Patent number 7,897,448
- Issue date Mar 1, 2011
- Lattice Semiconductor Corporation
- Sunil Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero-power programmable memory cell
- Patent number RE40311
- Issue date May 13, 2008
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- 365 - Static information storage and retrieval
Information Patent Grant
Circuit layout for improved performance while preserving or improvi...
- Patent number 7,301,182
- Issue date Nov 27, 2007
- Lattice Semiconductor Corporation
- Larry Metzger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM device with voltage-limiting charge pump circuit
- Patent number 7,242,053
- Issue date Jul 10, 2007
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for fabricating a semiconductor device having electrically...
- Patent number 7,078,286
- Issue date Jul 18, 2006
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-performance non-volatile memory device and fabrication process
- Patent number 6,977,408
- Issue date Dec 20, 2005
- Lattice Semiconductor Corp.
- Chih-Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voltage limited EEPROM device and process for fabricating the device
- Patent number 6,846,714
- Issue date Jan 25, 2005
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM device having an isolation-bounded tunnel capacitor and fabr...
- Patent number 6,841,447
- Issue date Jan 11, 2005
- Lattice Semiconductor Corporation
- Stewart Logie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device having electrically isolated low voltage and high voltage re...
- Patent number 6,833,602
- Issue date Dec 21, 2004
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Zero power memory cell with reduced threshold voltage
- Patent number 6,737,702
- Issue date May 18, 2004
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM device having a retrograde program junction region and proce...
- Patent number 6,716,705
- Issue date Apr 6, 2004
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero power memory cell with improved data retention
- Patent number 6,660,579
- Issue date Dec 9, 2003
- Lattice Semiconductor Corp.
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM device having improved data retention and process for fabric...
- Patent number 6,649,514
- Issue date Nov 18, 2003
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Zero-power programmable memory cell
- Patent number 6,611,463
- Issue date Aug 26, 2003
- Lattice Semiconductor Corporation
- Sunil Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM with a neutralized doping at tunnel window edge
- Patent number 6,600,188
- Issue date Jul 29, 2003
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow junction EEPROM device and process for fabricating the device
- Patent number 6,596,587
- Issue date Jul 22, 2003
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing process for borderless vias with respect to underlyin...
- Patent number 6,577,007
- Issue date Jun 10, 2003
- Advanced Micro Devices, Inc.
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complementary avalanche injection EEPROM cell
- Patent number 6,570,212
- Issue date May 27, 2003
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM tunnel window for program injection via P+ contacted...
- Patent number 6,545,313
- Issue date Apr 8, 2003
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combination of BPTEOS oxide film with CMP and RTA to achieve good d...
- Patent number 6,524,911
- Issue date Feb 25, 2003
- Lattice Semiconductor Corporation
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory cell with enhanced cell drive current
- Patent number 6,515,899
- Issue date Feb 4, 2003
- Lattice Semiconductor Corporation
- Robert Tu
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero-power logic cell for use in programmable logic devices
- Patent number 6,489,806
- Issue date Dec 3, 2002
- Lattice Semiconductor Corporation
- Sunil Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
Borderless vias on bottom metal
- Patent number 6,472,308
- Issue date Oct 29, 2002
- Advanced Micro Devices, Inc.
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing shallow trenches filled with dielectric m...
- Patent number 6,455,912
- Issue date Sep 24, 2002
- Vantis Corporation
- Hyeon-Seag Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eeprom tunnel window for program injection via P+ contacted...
- Patent number 6,455,375
- Issue date Sep 24, 2002
- Lattice Semiconductor Corporation
- Chun Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Floating gate memory apparatus and method for selected programming...
- Patent number 6,424,000
- Issue date Jul 23, 2002
- Vantis Corporation
- Sunil D. Mehta
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM cell with self-aligned tunneling window
- Patent number 6,424,003
- Issue date Jul 23, 2002
- Lattice Semiconductor Corporation
- Xiao Yu Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless vias on bottom metal
- Patent number 6,362,527
- Issue date Mar 26, 2002
- Advanced Micro Devices, Inc.
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Formation of high voltage transistor with high breakdown voltage
- Publication number 20080028521
- Publication date Feb 7, 2008
- Sunil Mehta
- G11 - INFORMATION STORAGE
Information Patent Application
Shallow trench isolation (STI) with trench liner of increased thick...
- Publication number 20070267715
- Publication date Nov 22, 2007
- Sunil Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polycide fuse with reduced programming time
- Publication number 20070111403
- Publication date May 17, 2007
- Chun Jiang
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated three-port receptacle and method for connecting hand and...
- Publication number 20070032789
- Publication date Feb 8, 2007
- Wayne J. Gonnering
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
Diode structure for word-line protection in a memory circuit
- Publication number 20060145238
- Publication date Jul 6, 2006
- Fabiano Fontana
- G11 - INFORMATION STORAGE
Information Patent Application
Process for fabricating a semiconductor device having an RTCVD layer
- Publication number 20060128162
- Publication date Jun 15, 2006
- Sunil D. Mehta
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
COMBINATION OF BPTEOS OXIDE FILM WITH CMP AND RTA TO ACHIEVE GOOD D...
- Publication number 20030036230
- Publication date Feb 20, 2003
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FARICATION OF HIGH QUALITY OXIDES BY CONTROLLING SPACING BETWEEN SE...
- Publication number 20020019143
- Publication date Feb 14, 2002
- HYEON-SEAG KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPROVING FIELD LEAKAGE BY USING A THIN LAYER OF NITRIDE DEPOSITED...
- Publication number 20020000626
- Publication date Jan 3, 2002
- Advanced Micro Devices, Inc.
- JONATHAN LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EEPROM CELL WITH SELF-ALIGNED TUNNELING WINDOW
- Publication number 20010042883
- Publication date Nov 22, 2001
- XIAO YU LI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate isolated triple-well non-volatile cell
- Publication number 20010022359
- Publication date Sep 20, 2001
- Sunil D. Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND SYSTEM FOR PROVIDING ELECTRICAL INSULATION FOR LOCAL INT...
- Publication number 20010014527
- Publication date Aug 16, 2001
- WILLIAM GEORGE EN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for fabricating semiconductor memory device with high data...
- Publication number 20010001075
- Publication date May 10, 2001
- Vantis Corporation
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS

Sunil D. Mehta

Person

Patents Grantslast 30 patents

Shallow trench isolation (STI) with trench liner of increased thick...

Shallow trench isolation (STI) with trench liner of increased thick...

Formation of high voltage transistor with high breakdown voltage

Zero-power programmable memory cell

Circuit layout for improved performance while preserving or improvi...

EEPROM device with voltage-limiting charge pump circuit

Process for fabricating a semiconductor device having electrically...

High-performance non-volatile memory device and fabrication process

Voltage limited EEPROM device and process for fabricating the device

EEPROM device having an isolation-bounded tunnel capacitor and fabr...

Device having electrically isolated low voltage and high voltage re...

Zero power memory cell with reduced threshold voltage

EEPROM device having a retrograde program junction region and proce...

Zero power memory cell with improved data retention

EEPROM device having improved data retention and process for fabric...

Zero-power programmable memory cell

EEPROM with a neutralized doping at tunnel window edge

Shallow junction EEPROM device and process for fabricating the device

Manufacturing process for borderless vias with respect to underlyin...

Complementary avalanche injection EEPROM cell

EEPROM tunnel window for program injection via P&#x0002B; contacted...

Combination of BPTEOS oxide film with CMP and RTA to achieve good d...

Non-volatile memory cell with enhanced cell drive current

Zero-power logic cell for use in programmable logic devices

Borderless vias on bottom metal

Process for manufacturing shallow trenches filled with dielectric m...

Eeprom tunnel window for program injection via P&#x0002B; contacted...

Floating gate memory apparatus and method for selected programming...

EEPROM cell with self-aligned tunneling window

Borderless vias on bottom metal

Patents Applicationslast 30 patents

Formation of high voltage transistor with high breakdown voltage

Shallow trench isolation (STI) with trench liner of increased thick...

Polycide fuse with reduced programming time

Integrated three-port receptacle and method for connecting hand and...

Diode structure for word-line protection in a memory circuit

Process for fabricating a semiconductor device having an RTCVD layer

COMBINATION OF BPTEOS OXIDE FILM WITH CMP AND RTA TO ACHIEVE GOOD D...

FARICATION OF HIGH QUALITY OXIDES BY CONTROLLING SPACING BETWEEN SE...

IMPROVING FIELD LEAKAGE BY USING A THIN LAYER OF NITRIDE DEPOSITED...

EEPROM CELL WITH SELF-ALIGNED TUNNELING WINDOW

Gate isolated triple-well non-volatile cell

METHOD AND SYSTEM FOR PROVIDING ELECTRICAL INSULATION FOR LOCAL INT...

Process for fabricating semiconductor memory device with high data...

EEPROM tunnel window for program injection via P+ contacted...

Eeprom tunnel window for program injection via P+ contacted...