Sunil Shenoy

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,944,817
- Issue date Aug 31, 1999
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a branch target buffer in CIS...
- Patent number 5,903,751
- Issue date May 11, 1999
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system employing streaming buffer for instruction preetching
- Patent number 5,870,599
- Issue date Feb 9, 1999
- Intel Corporation
- Glenn J. Hinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual prediction branch system having two step of branch recovery pr...
- Patent number 5,812,839
- Issue date Sep 22, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for predicting and handling resolving return f...
- Patent number 5,768,576
- Issue date Jun 16, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for using a direct memory access unit and a da...
- Patent number 5,749,092
- Issue date May 5, 1998
- Intel Corporation
- Jay Heeb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,706,492
- Issue date Jan 6, 1998
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for resolving return from subroutine instructi...
- Patent number 5,604,877
- Issue date Feb 18, 1997
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically expanding the pipeline of a mi...
- Patent number 5,590,368
- Issue date Dec 31, 1996
- Intel Corporation
- Jay Heeb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a set-associative branch targ...
- Patent number 5,574,871
- Issue date Nov 12, 1996
- Intel Corporation
- Bradley D. Hoyt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing bi-endian byte and short access...
- Patent number 5,574,923
- Issue date Nov 12, 1996
- Intel Corporation
- Jay Heeb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for an instruction cache locking scheme
- Patent number 5,493,667
- Issue date Feb 20, 1996
- Intel Corporation
- Scott B. Huck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for partial execution blocking of instructions...
- Patent number 5,455,924
- Issue date Oct 3, 1995
- Intel Corporation
- Sunil R. Shenoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High bandwith output hierarchical memory store including a cache, f...
- Patent number 5,313,605
- Issue date May 17, 1994
- Intel Corporation
- Scott Huck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and circuits for checking integrated circuit chips having p...
- Patent number 4,821,271
- Issue date Apr 11, 1989
- Intel Corporation
- M. Vittal Kini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable memory array control signals
- Patent number 4,785,428
- Issue date Nov 15, 1988
- Intel Corporation
- Atiq Bajwa
- G11 - INFORMATION STORAGE

Sunil Shenoy

Person

Patents Grantslast 30 patents

Method and apparatus for implementing a set-associative branch targ...

Method and apparatus for implementing a branch target buffer in CIS...

Computer system employing streaming buffer for instruction preetching

Dual prediction branch system having two step of branch recovery pr...

Method and apparatus for predicting and handling resolving return f...

Method and apparatus for using a direct memory access unit and a da...

Method and apparatus for implementing a set-associative branch targ...

Method and apparatus for resolving return from subroutine instructi...

Method and apparatus for dynamically expanding the pipeline of a mi...

Method and apparatus for implementing a set-associative branch targ...

Method and apparatus for performing bi-endian byte and short access...

Apparatus and method for an instruction cache locking scheme

Apparatus and method for partial execution blocking of instructions...

High bandwith output hierarchical memory store including a cache, f...

Methods and circuits for checking integrated circuit chips having p...

Programmable memory array control signals