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Suresh Balasubramanian
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Shrewsbury, MA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Frequency division clock alignment
Patent number
9,417,655
Issue date
Aug 16, 2016
Cavium, Inc.
Suresh Balasubramanian
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Frequency division clock alignment using pattern selection
Patent number
9,411,361
Issue date
Aug 9, 2016
Cavium, Inc.
Suresh Balasubramanian
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Clock distribution circuit with distributed delay locked loop
Patent number
9,335,784
Issue date
May 10, 2016
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Multi-function delay locked loop
Patent number
9,306,584
Issue date
Apr 5, 2016
Cavium, Inc.
David Lin
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Scannable flop with a single storage element
Patent number
9,264,023
Issue date
Feb 16, 2016
Cavium, Inc.
Suresh Balasubramanian
G01 - MEASURING TESTING
Information
Patent Grant
Multi-function delay locked loop
Patent number
9,143,140
Issue date
Sep 22, 2015
Cavium, Inc.
David Lin
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Multiplexer flop
Patent number
9,130,549
Issue date
Sep 8, 2015
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Clock gated delay line based on setting value
Patent number
8,963,601
Issue date
Feb 24, 2015
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
State machine for deskew delay locked loop
Patent number
8,513,994
Issue date
Aug 20, 2013
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Deterministic operation of an input/output interface
Patent number
7,568,118
Issue date
Jul 28, 2009
Intel Corporation
Warren R. Anderson
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Patents Applications
last 30 patents
Information
Patent Application
FREQUENCY DIVISION CLOCK ALIGNMENT USING PATTERN SELECTION
Publication number
20160142067
Publication date
May 19, 2016
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
FREQUENCY DIVISION CLOCK ALIGNMENT
Publication number
20160142066
Publication date
May 19, 2016
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Multi-Function Delay Locked Loop
Publication number
20150188528
Publication date
Jul 2, 2015
Cavium, Inc.
David Lin
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
MULTIPLEXER FLOP
Publication number
20150061741
Publication date
Mar 5, 2015
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Clock Gated Delay Line Based On Setting Value
Publication number
20150061743
Publication date
Mar 5, 2015
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
SCANNABLE FLOP WITH A SINGLE STORAGE ELEMENT
Publication number
20150061740
Publication date
Mar 5, 2015
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Distributed Delay Locked Loop
Publication number
20150067383
Publication date
Mar 5, 2015
Cavium, Inc.
Suresh Balasubramanian
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
STATE MACHINE FOR DESKEW DELAY LOCKED LOOP
Publication number
20120206178
Publication date
Aug 16, 2012
Cavium, Inc.
Suresh Balasubramanian
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
MULTI-FUNCTION DELAY LOCKED LOOP
Publication number
20120206181
Publication date
Aug 16, 2012
Cavium, Inc.
David Lin
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Deterministic operation of an input/output interface
Publication number
20070067514
Publication date
Mar 22, 2007
Warren R. Anderson
H04 - ELECTRIC COMMUNICATION TECHNIQUE