Suresh Venkatesan

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Separate layer formation in a semiconductor device
- Patent number 8,039,339
- Issue date Oct 18, 2011
- FREESCALE SEMICONDUCTOR, INC.
- John M. Grant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for mobility enhancement in a semiconductor de...
- Patent number 7,872,311
- Issue date Jan 18, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a semiconductor isolation trench
- Patent number 7,687,370
- Issue date Mar 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Toni D. Van Gompel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep STI trench and SOI undercut enabling STI oxide stressor
- Patent number 7,678,665
- Issue date Mar 16, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Michael D. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming an electronic device including semiconductor fins
- Patent number 7,456,055
- Issue date Nov 25, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for mobility enhancement in a semiconductor de...
- Patent number 7,288,448
- Issue date Oct 30, 2007
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory with recessed devices
- Patent number 7,078,297
- Issue date Jul 18, 2006
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming semiconductor device including interconnect barri...
- Patent number 6,713,381
- Issue date Mar 30, 2004
- Motorola, Inc.
- Alexander L. Barr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a copper interconnect using a multi-platen chemi...
- Patent number 6,573,173
- Issue date Jun 3, 2003
- Motorola, Inc.
- Janos Farkas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a dual inlaid copper interconnect structure
- Patent number 6,551,919
- Issue date Apr 22, 2003
- Motorola, Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a copper interconnect using a multi-platen chemi...
- Patent number 6,444,569
- Issue date Sep 3, 2002
- Motorola, Inc.
- Janos Farkas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device
- Patent number 6,362,057
- Issue date Mar 26, 2002
- Motorola, Inc.
- William J. Taylor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a dual inlaid copper interconnect structure
- Patent number 6,326,301
- Issue date Dec 4, 2001
- Motorola, Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a copper interconnect using a multi-platen chemi...
- Patent number 6,274,478
- Issue date Aug 14, 2001
- Motorola, Inc.
- Janos Farkas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an MOS transistor having a metallic gate electro...
- Patent number 5,960,270
- Issue date Sep 28, 1999
- Motorola, Inc.
- Veena Misra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a fully self-aligned soi mosfet
- Patent number 5,736,435
- Issue date Apr 7, 1998
- Motorola, Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making CMOS device having reduced parasitic capacitance
- Patent number 5,627,097
- Issue date May 6, 1997
- Motorola, Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having both vertical and horizontal devices and...
- Patent number 5,554,870
- Issue date Sep 10, 1996
- Motorola, Inc.
- Jon T. Fitch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a semiconductor device using dual planariza...
- Patent number 5,459,096
- Issue date Oct 17, 1995
- Motorola Inc.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE
- Publication number 20080261374
- Publication date Oct 23, 2008
- John M. Grant
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deep STI trench and SOI undercut enabling STI oxide stressor
- Publication number 20080220617
- Publication date Sep 11, 2008
- Freescale Semiconductor, Inc.
- Michael D. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR MOBILITY ENHANCEMENT IN A SEMICONDUCTOR DE...
- Publication number 20080006880
- Publication date Jan 10, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electronic device including a semiconductor fin and a process for f...
- Publication number 20070218628
- Publication date Sep 20, 2007
- Freescale Semiconductor, Inc.
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a semiconductor isolation trench
- Publication number 20070178661
- Publication date Aug 2, 2007
- Toni D. Van Gompel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS
- Publication number 20060194384
- Publication date Aug 31, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for mobility enhancement in a semiconductor de...
- Publication number 20060046366
- Publication date Mar 2, 2006
- Marius K. Orlowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device with multiple semiconductor layers
- Publication number 20050275018
- Publication date Dec 15, 2005
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory with recessed devices
- Publication number 20050266643
- Publication date Dec 1, 2005
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hetero-integration of semiconductor materials on silicon
- Publication number 20040012037
- Publication date Jan 22, 2004
- MOTOROLA, INC.
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a copper interconnect using a multi-platen chemi...
- Publication number 20020151167
- Publication date Oct 17, 2002
- Janos Farkas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method of formation
- Publication number 20020093098
- Publication date Jul 18, 2002
- Alexander L. Barr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a dual inlaid copper interconnect structure
- Publication number 20020039836
- Publication date Apr 4, 2002
- Suresh Venkatesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE CONDUCTIVE BUMP AND INTERCONNECT BARRIER
- Publication number 20020000665
- Publication date Jan 3, 2002
- ALEXANDER L. BARR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a copper interconnect using a multi-platen chemi...
- Publication number 20010027083
- Publication date Oct 4, 2001
- Janos Farkas
- H01 - BASIC ELECTRIC ELEMENTS

Suresh Venkatesan

Person

Patents Grantslast 30 patents

Separate layer formation in a semiconductor device

Method and apparatus for mobility enhancement in a semiconductor de...

Method of forming a semiconductor isolation trench

Deep STI trench and SOI undercut enabling STI oxide stressor

Process for forming an electronic device including semiconductor fins

Method and apparatus for mobility enhancement in a semiconductor de...

Memory with recessed devices

Method of forming semiconductor device including interconnect barri...

Method for forming a copper interconnect using a multi-platen chemi...

Method for forming a dual inlaid copper interconnect structure

Method for forming a copper interconnect using a multi-platen chemi...

Method for forming a semiconductor device

Method for forming a dual inlaid copper interconnect structure

Method for forming a copper interconnect using a multi-platen chemi...

Method for forming an MOS transistor having a metallic gate electro...

Process for fabricating a fully self-aligned soi mosfet

Method for making CMOS device having reduced parasitic capacitance

Integrated circuit having both vertical and horizontal devices and...

Process for fabricating a semiconductor device using dual planariza...

Patents Applicationslast 30 patents

SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE

Deep STI trench and SOI undercut enabling STI oxide stressor

METHOD AND APPARATUS FOR MOBILITY ENHANCEMENT IN A SEMICONDUCTOR DE...

Electronic device including a semiconductor fin and a process for f...

Method of forming a semiconductor isolation trench

SEMICONDUCTOR DEVICE WITH MULTIPLE SEMICONDUCTOR LAYERS

Method and apparatus for mobility enhancement in a semiconductor de...

Semiconductor device with multiple semiconductor layers

Memory with recessed devices

Hetero-integration of semiconductor materials on silicon

Method for forming a copper interconnect using a multi-platen chemi...

Semiconductor device and method of formation

Method for forming a dual inlaid copper interconnect structure

SEMICONDUCTOR DEVICE CONDUCTIVE BUMP AND INTERCONNECT BARRIER

Method for forming a copper interconnect using a multi-platen chemi...