Claims
- 1. A method for forming an interconnect comprising:forming an interconnect material over a semiconductor substrate, the interconnect material comprising a top bulk metal layer and a lower baffler layer; polishing an upper portion of the bulk metal layer at a first removal rate using a first platen; polishing a lower portion of the bulk metal layer at a second removal rate using a second platen wherein the first removal rate is greater tan the second removal rate and the second platen is different than the first platen; and polishing the baffler layer using a third platen.
- 2. The method of claim 1 wherein the interconnect material comprises primarily copper overlying a tantalum-containing barrier layer.
- 3. The method of claim 1 wherein the second platen supports an alumina slurry and the third platen supports an alumina slurry.
RELATED APPLICATIONS
This application is a divisional of application Ser. No. 09/835,276 filed on Apr. 16, 2001, entitled “A Method For Forming A Copper Interconnect Using A Multi-Platen Chemical Mechanical Polishing (CMP) Process” and assigned to the current assignee, now U.S. Pat. No. 6,444,569, which is a continuation of Ser. No. 09/532,136, filed on Jul. 13, 1999, entitled “A Method For Forming A Copper Interconnect Using A Multi-Platen Chemical Mechanical Polishing (CMP) Process” and assigned to the current assignee hereof, now U.S. Pat. No. 6,274,478.
US Referenced Citations (21)
Non-Patent Literature Citations (2)
Entry |
US 6,331,134, 12/2001, Sachan et al. (withdrawn) |
Chen et al., “The Investigation of Galvanic Corrosion in Post-Copper-CMP Cleaning,” IEEE 2000 International Interconnect Technology Conference, Jun. 5-7, 2000, pp. 256-258. |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/532136 |
Jul 1999 |
US |
Child |
09/835276 |
|
US |