Swaminathan Sivakumar

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three-dimensional memory arrays with layer selector transistors
- Patent number 12,114,479
- Issue date Oct 8, 2024
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 12,033,894
- Issue date Jul 9, 2024
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,972,979
- Issue date Apr 30, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Neighboring gate-all-around integrated circuit structures having di...
- Patent number 11,862,635
- Issue date Jan 2, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 11,854,787
- Issue date Dec 26, 2023
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 11,756,829
- Issue date Sep 12, 2023
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FIN shaping using templates and integrated circuit structures resul...
- Patent number 11,749,733
- Issue date Sep 5, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having oxide sub-fins
- Patent number 11,742,410
- Issue date Aug 29, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,721,580
- Issue date Aug 8, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,715,775
- Issue date Aug 1, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die interconnection scheme for providing a high yielding process fo...
- Patent number 11,652,060
- Issue date May 16, 2023
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin trim plug structures having an oxidation catalyst layer surroun...
- Patent number 11,538,937
- Issue date Dec 27, 2022
- Intel Corporation
- Leonard Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 11,495,496
- Issue date Nov 8, 2022
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Neighboring gate-all-around integrated circuit structures having di...
- Patent number 11,398,474
- Issue date Jul 26, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 11,373,950
- Issue date Jun 28, 2022
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures with gate-all-around...
- Patent number 11,355,608
- Issue date Jun 7, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin shaping using templates and integrated circuit structures resul...
- Patent number 11,302,790
- Issue date Apr 12, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory arrays with layer selector transistors
- Patent number 11,139,300
- Issue date Oct 5, 2021
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Grant
Pattern decomposition lithography techniques
- Patent number 11,107,786
- Issue date Aug 31, 2021
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dense memory arrays utilizing access transistors with back-side con...
- Patent number 11,056,492
- Issue date Jul 6, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 10,910,265
- Issue date Feb 2, 2021
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 10,892,223
- Issue date Jan 12, 2021
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 10,607,884
- Issue date Mar 31, 2020
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned isotropic etch of pre-formed vias and plugs for back e...
- Patent number 10,600,678
- Issue date Mar 24, 2020
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern decomposition lithography techniques
- Patent number 10,490,519
- Issue date Nov 26, 2019
- Intel Corporation
- Charles H. Wallace
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Exposure activated chemically amplified directed self-assembly (DSA...
- Patent number 10,459,338
- Issue date Oct 29, 2019
- Intel Corporation
- Paul A. Nyhus
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Pattern decomposition lithography techniques
- Patent number 10,409,152
- Issue date Sep 10, 2019
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate aligned contact and method to fabricate same
- Patent number 10,340,185
- Issue date Jul 2, 2019
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning of vertical nanowire transistor channel and gate with di...
- Patent number 10,325,814
- Issue date Jun 18, 2019
- Intel Corporation
- Paul A. Nyhus
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Self-aligned isotropic etch of pre-formed vias and plugs for back e...
- Patent number 10,211,088
- Issue date Feb 19, 2019
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
- Publication number 20240389300
- Publication date Nov 21, 2024
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME
- Publication number 20240282633
- Publication date Aug 22, 2024
- Intel Corporation
- Oleg GOLONZKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DI...
- Publication number 20240088142
- Publication date Mar 14, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FULL WAFER DEVICE WITH MULTIPLE DIRECTIONAL INDICATORS
- Publication number 20240071955
- Publication date Feb 29, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES
- Publication number 20240071917
- Publication date Feb 29, 2024
- Intel Corporation
- Richard E. SCHENKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STATIC RANDOM-ACCESS MEMORY DEVICES WITH ANGLED TRANSISTORS
- Publication number 20230422463
- Publication date Dec 28, 2023
- Intel Corporation
- Abhishek A. Sharma
Information Patent Application
GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME
- Publication number 20230360972
- Publication date Nov 9, 2023
- Intel Corporation
- Oleg GOLONZKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS
- Publication number 20230352561
- Publication date Nov 2, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG
- Publication number 20230326794
- Publication date Oct 12, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FO...
- Publication number 20230245974
- Publication date Aug 3, 2023
- Intel Corporation
- Wilfred GOMES
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DELIVERY USING BACKSIDE POWER FOR STITCHED DIES
- Publication number 20230207565
- Publication date Jun 29, 2023
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COOLING APPROACHES FOR STITCHED DIES
- Publication number 20230209800
- Publication date Jun 29, 2023
- Abhishek Anil SHARMA
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH BANDWIDTH AND CAPACITY APPROACHES FOR STITCHED DIES
- Publication number 20230207445
- Publication date Jun 29, 2023
- Abhishek Anil SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN TRIM PLUG STRUCTURES HAVING AN OXIDATION CATALYST LAYER SURROUN...
- Publication number 20230089815
- Publication date Mar 23, 2023
- Intel Corporation
- Leonard GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME
- Publication number 20230030806
- Publication date Feb 2, 2023
- Intel Corporation
- Oleg GOLONZKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DI...
- Publication number 20220320085
- Publication date Oct 6, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES
- Publication number 20220262722
- Publication date Aug 18, 2022
- Intel Corporation
- Richard E. SCHENKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...
- Publication number 20220254893
- Publication date Aug 11, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...
- Publication number 20220199792
- Publication date Jun 23, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES
- Publication number 20210375807
- Publication date Dec 2, 2021
- Intel Corporation
- CHARLES H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
- Publication number 20210335791
- Publication date Oct 28, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CON...
- Publication number 20210193666
- Publication date Jun 24, 2021
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS
- Publication number 20210151438
- Publication date May 20, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME
- Publication number 20210125866
- Publication date Apr 29, 2021
- Intel Corporation
- Oleg GOLONZKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES
- Publication number 20210082800
- Publication date Mar 18, 2021
- Intel Corporation
- Richard E. SCHENKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...
- Publication number 20200388689
- Publication date Dec 10, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG
- Publication number 20200388534
- Publication date Dec 10, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN TRIM PLUG STRUCTURES FOR IMPARTING CHANNEL STRESS
- Publication number 20200220016
- Publication date Jul 9, 2020
- Intel Corporation
- Leonard GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS
- Publication number 20200219978
- Publication date Jul 9, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FO...
- Publication number 20200211970
- Publication date Jul 2, 2020
- Intel Corporation
- Wilfred GOMES
- H01 - BASIC ELECTRIC ELEMENTS

Swaminathan Sivakumar

Person

Patents Grantslast 30 patents

Three-dimensional memory arrays with layer selector transistors

Gate aligned contact and method to fabricate same

1D vertical edge blocking (VEB) via and plug

Neighboring gate-all-around integrated circuit structures having di...

Advanced lithography and self-assembled devices

Gate aligned contact and method to fabricate same

FIN shaping using templates and integrated circuit structures resul...

Gate-all-around integrated circuit structures having oxide sub-fins

1D vertical edge blocking (VEB) via and plug

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Die interconnection scheme for providing a high yielding process fo...

Fin trim plug structures having an oxidation catalyst layer surroun...

Gate aligned contact and method to fabricate same

Neighboring gate-all-around integrated circuit structures having di...

Advanced lithography and self-assembled devices

Self-aligned gate endcap (SAGE) architectures with gate-all-around...

Fin shaping using templates and integrated circuit structures resul...

Three-dimensional memory arrays with layer selector transistors

Pattern decomposition lithography techniques

Dense memory arrays utilizing access transistors with back-side con...

Gate aligned contact and method to fabricate same

Advanced lithography and self-assembled devices

Gate aligned contact and method to fabricate same

Self-aligned isotropic etch of pre-formed vias and plugs for back e...

Pattern decomposition lithography techniques

Exposure activated chemically amplified directed self-assembly (DSA...

Pattern decomposition lithography techniques

Gate aligned contact and method to fabricate same

Patterning of vertical nanowire transistor channel and gate with di...

Self-aligned isotropic etch of pre-formed vias and plugs for back e...

Patents Applicationslast 30 patents

THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS

GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME

NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DI...

FULL WAFER DEVICE WITH MULTIPLE DIRECTIONAL INDICATORS

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

STATIC RANDOM-ACCESS MEMORY DEVICES WITH ANGLED TRANSISTORS

GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS

1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG

DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FO...

POWER DELIVERY USING BACKSIDE POWER FOR STITCHED DIES

COOLING APPROACHES FOR STITCHED DIES

HIGH BANDWIDTH AND CAPACITY APPROACHES FOR STITCHED DIES

FIN TRIM PLUG STRUCTURES HAVING AN OXIDATION CATALYST LAYER SURROUN...

GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME

NEIGHBORING GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DI...

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND...

FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...

PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES

THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS

DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CON...

THREE-DIMENSIONAL MEMORY ARRAYS WITH LAYER SELECTOR TRANSISTORS

GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

FIN SHAPING USING TEMPLATES AND INTEGRATED CIRCUIT STRUCTURES RESUL...

1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG

FIN TRIM PLUG STRUCTURES FOR IMPARTING CHANNEL STRESS

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING OXIDE SUB-FINS

DIE INTERCONNECTION SCHEME FOR PROVIDING A HIGH YIELDING PROCESS FO...