Patent Application
20250159953
For the past several decades, the scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each contact becomes increasingly significant. Careful design of transistors may help with such an optimization.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
IC devices with angled transistors, and related assemblies and methods, are disclosed herein. The devices, assemblies, and methods of this disclosure each have several innovative aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating IC devices with angled transistors, proposed herein, it might be useful to first understand phenomena that may come into play in such arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
A field-effect transistor (FET), e.g., a metal-oxide-semiconductor (MOS) FET (MOSFET), is a three-terminal device that includes source, drain, and gate terminals and uses electric field to control current flowing through the device. A FET typically includes a semiconductor channel material, a source region and a drain region provided in the channel material, and a gate stack that includes at least a gate electrode material and, optionally, may also include a gate insulator, where the gate stack is provided over a portion of the channel material between the source region and the drain region.
Recently, FETs with non-planar architectures, such as FinFETs (also sometimes referred to as “wrap around gate transistors” or “tri-gate transistors”) and nanoribbon/nanowire transistors (also sometimes referred to as “gate all-around (GAA) transistors”), have been extensively explored as alternatives to transistors with planar architectures.
In a FinFET, an elongated semiconductor structure (i.e., an elongated structure that includes a semiconductor material) shaped as a fin extends away from a base (e.g., from a semiconductor substrate or any suitable support structure). A portion of a fin that is closest to the base may be enclosed by an insulator material. Such an insulator material, typically an oxide, is commonly referred to as a “shallow trench isolation” (STI), and the portion of the fin enclosed by the STI is referred to as a “subfin portion” or simply a “subfin.” A gate stack may wrap around an upper portion of the fin (i.e., the portion farthest away from the base). The portion of the fin around which the gate stack wraps is referred to as a “channel” or a “channel portion” of a FinFET. A semiconductor material of the channel portion is commonly referred to as a “channel material” of the transistor. FinFETs are sometimes referred to as “tri-gate transistors” because, in use, such transistors may form conducting channels on three “sides” of the channel portion of the fin. A source region and a drain region are provided in the fin on the opposite sides of the gate stack, forming, respectively, a source and a drain of a FinFET.
In a nanoribbon transistor, a gate stack may be provided around a portion of an elongated semiconductor structure called “nanoribbon”, forming a gate on all sides of the nanoribbon. The “channel” or the “channel portion” of a nanoribbon transistor is the portion of the nanoribbon around which the gate stack wraps. Such transistors are sometimes referred to as “GAA transistors” because, in use, such transistors may form conducting channels on all “sides” of the channel portion of the nanoribbon. A source region and a drain region are provided in the nanoribbon on each side of the gate stack, forming, respectively, a source and a drain of a nanoribbon transistor. In some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure that has a substantially rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but with a substantially circular or square transverse cross-sections. In the following, a single term “nanoribbon transistor” is used to describe all non-planar transistors where a gate stack wraps around substantially all sides of an elongated semiconductor structure, independent of the shape of the transverse cross-section. Thus, as used herein, the term “nanoribbon transistor” is used to cover transistors with elongated semiconductor structures that have substantially rectangular transverse cross-sections (possibly with rounded corners), transistors with elongated semiconductor structures that have substantially square transverse cross-sections (possibly with rounded corners), transistors with elongated semiconductor structures that have substantially circular or elliptical/oval transverse cross-sections, as well as transistors with elongated semiconductor structures that have any polygonal transverse cross-sections.
As the foregoing illustrates, both FinFETs and nanoribbon transistors are built based on elongated semiconductor structures. A longitudinal axis of such structures may be defined as a line that is the shortest line between a source region and a drain region of a FinFET or a nanoribbon transistor. Typically, such a line extends substantially parallel to a support structure (e.g., a die, a chip, a substrate, a carrier substrate, or a package substrate) on/in which a transistor resides and is one of lines of symmetry for the transistor (at least for the idealized version of the transistor that does not reflect unintended manufacturing variations that may affect the real-life geometry of the transistor). Conventionally, FinFETs and nanoribbon transistors are oriented on a support structure so that the longitudinal axes of their elongated semiconductor structures (i.e., fins or nanoribbons, respectively) are parallel to the front and back faces of the support structure and are either perpendicular or parallel to different edges of the support structure, in particular, being either perpendicular or parallel to different edges of the front face or the back face of the support structure. In contrast to such conventional implementations, embodiments of the present disclosure provide IC devices with angled transistors, where a transistor is referred to as “angled” if a longitudinal axis of the elongated semiconductor structure based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on/in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of the edges of front or back faces of the support structure (since not just one but two angles may be defined among any two lines crossing one another, the two angles adding together to be 180 degrees, for the angled structures/transistors, angles referred to herein refer to the smaller of the two angles for any given pair of two lines). Angled transistors provide a promising way to increasing densities of transistors, in particular, of FinFETs and nanoribbon transistors, on the limited real estate of semiconductor chips, and embodiments of the present disclosure provide solutions for layout and patterning of angled transistors, as well as for integration of angled and non-angled transistors.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, in context of source/drain (S/D) regions, the term “region” may be used interchangeably with the terms “contact” and “terminal” of a transistor. In another example, as used herein, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” “sulfide,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, sulfur, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−1-20% of a target value, e.g., +/−1-10% of a target value or +/−1-5% of a target value, based on the context of a particular value as described herein or as known in the art.
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, analogous elements designated in the present drawings with different reference numerals after a dash, e.g., edges 303-1, 303-2, 303-3, and 303-4 may be collectively referred to together without the reference numerals after the dash, e.g., as “edges 303.” In order to not clutter the drawings, if multiple instances of certain elements are illustrated, only some of the elements may be labeled with a reference sign. A plurality of drawings with the same number and different letters may be referred to without the letters, e.g.,
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC devices with angled transistors as described herein.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Various IC devices with angled transistors as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
Turning to the details of
The IC device 100 shown in
Implementations of the present disclosure may be formed or carried out on any suitable support structure 102, such as a substrate, a die, a wafer, or a chip. The support structure 102 may, e.g., be the wafer 2000 of
The nanoribbon 104 may take the form of a nanowire or nanoribbon, for example. In some embodiments, an area of a transverse cross-section of the nanoribbon 104 (i.e., an area in the x-z plane of the example coordinate system x-y-z shown in
Although the nanoribbon 104 illustrated in
The nanoribbon 104 may be formed of one or more semiconductor materials, together referred to as a “channel material.” In general, channel materials of any of the angled transistors described herein, e.g., the channel material of the transistor 110, may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the channel material may include a substantially monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from group Ill of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a combination of semiconductor materials.
For some example N-type transistor embodiments (i.e., for the embodiments where the transistor in which the channel material is included is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material may include a Ill-V material having a relatively high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). For some example P-type transistor embodiments (i.e., for the embodiments where the transistor in which the channel material is included is a P-type metal-oxide-semiconductor (PMOS) transistor), the channel material may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.
In some embodiments, the channel material may be a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc.
As noted above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, e.g., in the range of 20-50 times than amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low fabrication cost relative to other semiconductors. IGZO can be deposited as a uniform amorphous phase while retaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula InGaO3(ZnO)5. Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain tertiary dopants such as aluminum or nitrogen.
In some embodiments, any of the angled transistors described herein, e.g., the transistor 110, may be a thin-film transistor (TFT). A TFT is a special kind of a FET made by depositing active semiconductor material over a support (e.g., a support structure as described above) that may be a non-conducting support. Some such materials may be deposited at relatively low temperatures, which allows depositing them within the thermal budgets imposed on back-end fabrication to avoid damaging the front-end components such as the logic devices of an IC device in which the transistor may be included. Thus, in some embodiments, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may be a semiconductor material deposited at relatively low temperatures, and may include any of the oxide semiconductor materials described above.
In other embodiments, instead of being deposited at relatively low temperatures as described above with reference to the TFTs, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may be epitaxially grown in what typically involves relatively high-temperature processing. In such embodiments, the channel material may include any of the semiconductor materials described above, including oxide semiconductor materials. In some such embodiments, the channel material may be epitaxially grown directly on a semiconductor layer of a support structure over which the transistor will be fabricated, in a process known as “monolithic integration.” In other such embodiments, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may be epitaxially grown on a semiconductor layer of another support structure and then the epitaxially grown layer of the channel material may be transferred, in a process known as a “layer transfer,” to a support structure over which the transistor will reside, in which case the latter support structure may but does not have to include a semiconductor layer prior to the layer transfer. Layer transfer advantageously allows forming non-planar transistors, such as FinFETs or nanoribbon transistors, over support structures or in layers that do not include semiconductor materials (e.g., in the back end of an IC device). Layer transfer also advantageously allows forming transistors of any architecture (e.g., non-planar or planar transistors) without imposing the negative effects of the relatively high-temperature epitaxial growth process on devices that may already be present over a support structure.
A channel material that is deposited at relatively low temperatures is typically a polycrystalline, polymorphous, or amorphous semiconductor, or any combination thereof. A channel material that is epitaxially grown is typically a highly crystalline (e.g., monocrystalline or single-crystalline) material. Therefore, whether the channel material of any of the angled transistors described herein, e.g., the transistor 110, is deposited at relatively low temperatures or epitaxially grown can be identified by inspecting grain size of the active portions of the channel material (e.g., of the portions of the channel material that form channels of transistors). An average grain size of a channel material of any of the angled transistors described herein, e.g., the transistor 110, being between about 0.5 and 1 millimeters (in which case the material may be polycrystalline) or smaller than about 0.5 millimeter (in which case the material may be polymorphous or amorphous) may be indicative of the channel material having been deposited (e.g., in which case the transistors in which such a channel material is included are TFTs). On the other hand, an average grain size of a channel material of any of the angled transistors described herein, e.g., the transistor 110, being equal to or greater than about 1 millimeter (in which case the material may be a single-crystal material) may be indicative of the channel material having been epitaxially grown and included in the final device either by monolithic integration or by layer transfer.
In some embodiments, the channel material of any of the angled transistors described herein, e.g., the transistor 110, may include a two-dimensional (2D) semiconductor material, i.e., a semiconductor material with a thickness of a few nanometers or less, where electrons in the material are free to move in the 2D plane but their restricted motion in the third direction is governed by quantum mechanics. In some such embodiments, such a channel material may include a single atomic monolayer of a 2D semiconductor material, while, in other such embodiments, such a channel material may include five or more atomic monolayers of a 2D semiconductor material. Examples of 2D materials that may be used to implement the channel material of any of the angled transistors described herein include, but are not limited to, graphene, hexagonal boron nitride, or transition-metal chalcogenides.
A gate stack 106 including a gate electrode material 108 and, optionally, a gate insulator 112, may wrap entirely or almost entirely around a portion of the nanoribbon 104 as shown in
The gate electrode material 108 may include at least one P-type work function metal or N-type work function metal, depending on whether the transistor 110 is a PMOS transistor or an NMOS transistor. P-type work function metal may be used as the gate electrode material 108 when the transistor 110 is a PMOS transistor and N-type work function metal may be used as the gate electrode material 108 when the transistor 110 is an NMOS transistor. For a PMOS transistor, metals that may be used for the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further layers may be included next to the gate electrode material 108 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
In some embodiments, the gate insulator 112 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, an annealing process may be carried out on the gate insulator 112 during manufacture of the transistor 110 to improve the quality of the gate insulator 112. The gate insulator 112 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers), although, in other embodiments, the thickness of the gate insulator 112 may be greater than 3 nanometers. In some embodiments, the gate stack 106 may be surrounded by a gate spacer, not shown in
In some embodiments, the gate insulator 112 may include a hysteretic material or a hysteretic arrangement, which, together, may be referred to as a “hysteretic element.” Transistors 110 in which the gate insulator 124 includes a hysteretic element may be described as “hysteretic transistors” and may be used to implement hysteretic memory. Hysteretic memory refers to a memory technology employing hysteretic materials or arrangements, where a material or an arrangement may be described as hysteretic if it exhibits the dependence of its state on the history of the material (e.g., on a previous state of the material). Ferroelectric (FE) and antiferroelectric (AFE) materials are examples of hysteretic materials. Layers of different materials arranged in a stack to exhibit charge-trapping phenomena is an example of a hysteretic arrangement.
A FE or an AFE material is a material that exhibits, over some range of temperatures, spontaneous electric polarization, i.e., displacement of positive and negative charges from their original position, where the polarization can be reversed or reoriented by application of an electric field. In particular, an AFE material is a material that can assume a state in which electric dipoles from the ions and electrons in the material may form a substantially ordered (e.g., substantially crystalline) array, with adjacent dipoles being oriented in opposite (antiparallel) directions (i.e., the dipoles of each orientation may form interpenetrating sub-lattices, loosely analogous to a checkerboard pattern), while a FE material is a material that can assume a state in which all of the dipoles point in the same direction. Because the displacement of the charges in FE and AFE materials can be maintained for some time even in the absence of an electric field, such materials may be used to implement memory cells. Because the current state of the electric dipoles in FE and AFE materials depends on the previous state, such materials are hysteretic materials. Memory technology where logic states are stored in terms of the orientation of electric dipoles in (i.e., in terms of polarization of) FE or AFE materials is referred to as “FE memory,” where the term “ferroelectric” is said to be adopted to convey the similarity of FE memories to ferromagnetic memories, even though there is typically no iron (Fe) present in FE or AFE materials.
A stack of alternating layers of materials that is configured to exhibit charge-trapping is an example of a hysteretic arrangement. Such a stack may include as little as two layers of materials, one of which is a charge-trapping layer (i.e., a layer of a material configured to trap charges when a voltage is applied across the material) and the other one of which is a tunnelling layer (i.e., a layer of a material through which the charge is to be tunneled to the charge-trapping layer). The tunnelling layer may include an insulator material such as a material that includes silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include a metal or a semiconductor material that is configured to trap charges. Because the trapped charges may be kept in a charge-trapping arrangement for some time even in the absence of an electric field, such arrangements may be used to implement memory cells. Because the presence and/or the number of trapped charges in a charge-trapping arrangement depends on the previous state, such arrangements are hysteretic arrangements. Memory technology where logic states are stored in terms of the amount of charge trapped in a hysteretic arrangement may be referred to as “charge-trapping memory.”
Hysteretic memories have the potential for adequate non-volatility, short programming time, low power consumption, high endurance, and high-speed writing. In addition, hysteretic memories may be manufactured using processes compatible with the standard complementary metal-oxide-semiconductor (CMOS) technology. Therefore, over the last few years, these types of memories have emerged as promising candidates for many growing applications.
In some embodiments, the hysteretic element of the gate insulator 112 may be provided as a layer of a FE or an AFE material. Such an FE/AFE material may include one or more materials that can exhibit sufficient FE/AFE behavior even at thin dimensions, e.g., such as an insulator material at least about 5%, e.g., at least about 7% or at least about 10%, of which is in an orthorhombic phase and/or a tetragonal phase (e.g., as a material in which at most about 95-90% of the material may be amorphous or in a monoclinic phase). For example, such materials may be based on hafnium and oxygen (e.g., hafnium oxides), with various dopants added to ensure sufficient amount of an orthorhombic phase or a tetragonal phase. Some examples of such materials include materials that include hafnium, oxygen, and zirconium (e.g., hafnium zirconium oxide (HfZrO, also referred to as HZO)), materials that include hafnium, oxygen, and silicon (e.g., silicon-doped (Si-doped) hafnium oxide), materials that include hafnium, oxygen, and germanium (e.g., germanium-doped (Ge-doped) hafnium oxide), materials that include hafnium, oxygen, and aluminum (e.g., aluminum-doped (Al-doped) hafnium oxide), and materials that include hafnium, oxygen, and yttrium (e.g., yttrium-doped (Y-doped) hafnium oxide). However, in other embodiments, any other materials which exhibit FE/AFE behavior at thin dimensions may be used as the hysteretic element and are within the scope of the present disclosure.
In other embodiments, the hysteretic element of the gate insulator 112 may be provided as a stack of alternating layers of materials that can trap charges. In some such embodiments, the stack may be a two-layer stack, where one layer is a charge-trapping layer and the other layer is a tunnelling layer. The tunnelling layer may include an insulator material such as a material that includes silicon and oxygen (e.g., silicon oxide), or any other suitable insulator. The charge-trapping layer may include an electrically conductive material such as a metal, or a semiconductor material. In some embodiments, the charge-trapping layer may include a sub-stoichiometric material (i.e., a material that includes less than a stochiometric amount of a reagent). The sub-stoichiometric material may include vacancies in concentration of at least about 1018 vacancies per cubic centimeter, e.g., in concentration between about 1018 vacancies per cubic centimeter and about 1022-1023 vacancies per cubic centimeter. As known in the art, vacancies refer to cites where atoms (e.g., oxygen or nitrogen) that should be present are missing, thus providing a defect in a material. For example, the sub-stoichiometric material of any of the hysteretic elements described herein may include oxygen and the vacancies may be oxygen vacancies, or the sub-stoichiometric material may include nitrogen and the vacancies may be nitrogen vacancies. During operation, charges may be trapped in the vacancies of the sub-stoichiometric material. Thus, implementing a sub-stoichiometric material with vacancies is one way to provide a charge-trapping layer of a hysteretic arrangement. In general, any material that has defects that can trap charge may be used in/as a charge-trapping layer. Such defects are very detrimental to operation of logic devices and, therefore, typically, deliberate steps need to be taken to avoid presence of the defects. However, for memory devices, such defects are desirable because charge-trapping may be used to represent different memory states of a memory cell.
In some embodiments of the hysteretic element being provided as a stack of alternating layers of materials that can trap charges, the stack may be a three-layer stack where an insulator material is provided on both sides of a charge-trapping layer. In such embodiments, a layer of an insulator material on one side of the charge-trapping layer may be referred to as a “tunnelling layer” while a layer of an insulator material on the other side of the charge-trapping layer may be referred to as a “field layer.”
In various embodiments of the hysteretic element being provided as a stack of alternating layers of materials that can trap charges, a thickness of each layer the stack may be between about 0.5 and 10 nanometers, including all values and ranges therein, e.g., between about 0.5 and 5 nanometers. In some embodiment of a three-layer stack, a thickness of each layer of the insulator material may be about 0.5 nanometers, while a thickness of the charge-trapping layer may be between about 1 and 8 nanometers, e.g., between about 2.5 and 7.5 nanometers, e.g., about 5 nanometers. In some embodiments, a total thickness of the hysteretic element provided as a stack of alternating layers of materials that can trap charges (i.e., a hysteretic arrangement) may be between about 1 and 10 nanometers, e.g., between about 2 and 8 nanometers, e.g., about 6 nanometers.
Turning to the S/D regions 114 of the transistor 110, in some embodiments, the S/D regions may be highly doped, e.g., with dopant concentrations of about 1021 dopants per cubic centimeter, in order to advantageously form Ohmic contacts with the respective S/D electrodes, although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the S/D regions of a transistor may be the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in the channel portion (i.e., in a channel material extending between the first S/D region 114-1 and the second S/D region 114-2), and, therefore, may be referred to as “highly doped” (HD) regions. The channel portion of the transistor 110 may include semiconductor materials with doping concentrations significantly smaller than those of the S/D regions 114.
The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104 may follow the ion implantation process. In the latter process, portions of the nanoribbon 104 may first be etched to form recesses at the locations of the future S/D regions 114. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 114. In some implementations, the S/D regions 114 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions 114 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 114. In some embodiments, a distance between the first and second S/D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).
In some embodiments, angled transistors described herein may be implemented in memory arrays. In some such embodiments, an angled transistor may be coupled to a storage element, thus forming a 1T-1X memory cell of a memory array, where “1T” in the term “1T-1X memory cell” indicates that the memory cell includes one transistor (T), and where “1X” in the term “1T-1X memory cell” indicates that the memory cell includes one storage element (X). In other embodiments, an angled transistor may be coupled to multiple storage elements, or an angled transistor may be coupled to another transistor, to form one or more memory cells of a memory array, all of which being within the scope of the present disclosure. Generally, a storage element may be any suitable IC component that can be programmed to a target data state (e.g., corresponding to a particular charged stored on the storage element or corresponding to a particular resistance state of the storage element) by applying an electric field or energy (e.g., positive or negative voltage or current pulses) to the storage element for a particular duration. In various embodiments, a storage element may be a capacitor, a resistive storage element, a resistive random-access memory (RRAM) device, a metal filament memory device, a phase change memory (PCM) device, a magnetic random-access memory (MRAM) device, etc.
An example of using the transistor 110 as a part of a memory cell is illustrated in
As an example, a dynamic random-access memory (DRAM) cell may include a storage element 166 in a form of a capacitor for storing a bit value, or a memory state (e.g., logical “1” or “0”) of the cell, and an access transistor, implemented as the transistor 110, controlling access to the cell (e.g., access to write information to the cell or access to read information from the cell). Such a memory cell may be referred to as a “1T-1C memory cell,” highlighting the fact that it uses one transistor (i.e., “1T” in the term “1T-1C memory cell”) and one capacitor (i.e., “1C” in the term “1T-1C memory cell”). In such embodiments, the electrodes 167 may be capacitor electrodes, and the memory material 169 may be a capacitor insulator. In some embodiments, the memory material 169 of such a capacitor may be a dielectric material. In other embodiments, the memory material 169 of such a capacitor may be a hysteretic element, e.g., as described above with reference to the embodiments where the gate insulator 112 is a hysteretic element.
In another example, the storage element 166 may be a resistive storage element (also referred to herein as a “resistive switch”) that includes the memory material 169 that is a resistance-changing material, i.e., during operation the memory material 169 can be switched between two different nonvolatile states: a high resistance state (HRS) and a low resistance state (LRS). The state of a resistive storage element may be used to represent a data bit (e.g., logical “1” for HRS and logical “0” for LRS, or vice versa). A resistive storage element may have a voltage threshold beyond which the resistive storage element is in the LRS; driving a resistive storage element into the LRS may be referred to as SET (with an associated SET threshold voltage). Similarly, a resistive storage element may have a voltage threshold beyond which the resistive storage element is in the HRS; driving a resistive storage element into the HRS may be referred to as RESET (with an associated RESET threshold voltage).
In another example, the storage element 166 may be a RRAM device; in such embodiments, the memory material 169 may include an oxygen exchange layer (e.g., hafnium) and an oxide layer, as known in the art.
In yet another example, the storage element 166 may be a metal filament memory device (e.g., a conductive bridging random-access memory (CBRAM) device); in such embodiments, the memory material 169 may include a solid electrolyte, and one of the electrodes 167 of the storage element 166 may be an electrochemically active material (e.g., silver or copper), and the other of the electrodes 167 of the storage element 166 may be an inert material (e.g., an inert metal), as known in the art. A chemical barrier layer (e.g., tantalum, tantalum nitride, or tungsten) may be disposed between the electrochemically active electrode and the solid electrolyte to mitigate diffusion of the electrochemically active material into the solid electrolyte, in some such embodiments.
In some embodiments, the storage element 166 may be a PCM device; in such embodiments, the memory material 169 may include a chalcogenide or other phase change memory material.
In some embodiments, the storage element 166 may be a MRAM device; in such embodiments, the memory material 169 may include a thin tunnel barrier material, and the electrodes 167 of the storage element 166 may be magnetic (e.g., ferromagnetic). As known in the art, MRAM devices may operate on the principle of tunnel magnetoresistance between two magnetic layers (e.g., the electrodes of the storage element 166) separated by a tunnel junction (e.g., the memory material of the storage element 166). An MRAM device may have two stable states: when the magnetic moments of the two magnetic layers are aligned parallel to each other, an MRAM device may be in the LRS, and when aligned antiparallel, an MRAM device may be in the HRS.
The IC device 200 shown in
Turning to the details of
A longitudinal axis 220 of the fin 204 may be along the y-axis of the example coordinate system shown in the present drawings. The FinFET 210 may have a gate length (i.e., a distance between the first and second S/D regions 214-1, 214-2), a dimension measured along the longitudinal axis 220, which may, in some embodiments, be between 2 and 60 nanometers, including all values and ranges therein (e.g., between 5 and 20 nanometers, or between 5 and 30 nanometers). Although the fin 204 is illustrated in
An example of using the FinFET 210 as a part of a memory cell is illustrated in
Either the nanoribbon 104 or the fin 204 may be an elongated semiconductor structure based on which any of the angled transistors described herein may be built (i.e., any of the angled transistors may be implemented as, e.g., the transistor 110 or the FinFET 210). Differences between non-angled elongated semiconductor structures and angled elongated semiconductor structures are described with reference to
The IC devices 300 shown in
As shown in
As shown in
As shown in
In various embodiments, both the non-angled elongated semiconductor structures 304 and the angled elongated semiconductor structures 306 may be provided over a single support structure 302, with some examples of such embodiments shown in
In order to not clutter the drawings, the details of the non-angled layer 314 and the angled layer 316 are only shown in
In some embodiments of the IC device 310 of
The embodiments of
The IC devices 324 shown in
In various embodiments, the angled elongated semiconductor structures 306 may be fabricated by, first, forming longer angled elongated semiconductor structures of suitable semiconductor materials and then cutting or/and trimming the longer structures to form various angled elongated semiconductor structures 306 as described herein. For example, each of
Turning to the details of line patterning,
The IC device 324 shown in
One or more cut lines 330 defined by the boundaries of a pair of lines 332-1 and 332-2 shown in
Besides using cut lines 330, in some embodiments, cut vias 340 may be used, e.g., as illustrated in
Cut lines 330 and cut vias 340 illustrated in
IC devices with angled transistors, disclosed herein, may be manufactured using any suitable techniques. For example,
The IC devices shown in
Although the operations of the manufacturing methods illustrated in
The substantially straight portions of the angled elongated semiconductor structures 366 of the IC device 350D may then serve as the angled elongated semiconductor structures that may be patterned to form angled transistors as described above. However, having the loops at the first ends 362-1 and at the second ends 362-2 of the angled elongated semiconductor structures 366 is not desirable. Therefore,
A plurality of the U-shaped loop portions of the semiconductor material that is substantially the same as that of the substantially straight portions 367 of the angled elongated semiconductor structures 366 at the first ends 362-1 and a similar plurality of the U-shaped loop portions at the second ends 362-2 would be detectable in the final structures as U-shaped portions of semiconductor materials not electrically connected to anything, just remaining in the final device as consequences of using the loop trimming method as described herein. Thus, in some embodiments, these U-shaped portions of semiconductor materials may be enclosed by an insulator material on all sides.
As a result of the patterning of
In some embodiments, in a direction of longitudinal axes of the angled elongated semiconductor structures 366 (such as the longitudinal axes 320, described above), a dimension of such U-shaped loop portions either at the first ends 362-1 or at the second ends 362-2 would be, at most, 10% of the length of the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2. Projections of the U-shaped loop portions of the semiconductor material onto the support structure 302 may be curves, which would be very distinct from the analogous projections of the substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2, which would be rectangles. In some embodiments, a width of any of the cut lines 368 may be between about 3 nanometers and 1000 nanometers, e.g., between about 5 nanometers and 100 nanometers, or between about 10 nanometers and 75 nanometers.
The substantially straight portions 367 of the angled elongated semiconductor structures 366 between the first ends 362-1 and the second ends 362-2 may subsequently be patterned according to different patterning techniques, e.g., as described with reference to
In the loop trimming method as described above, the backbone material 354 may include any material that is sufficiently etch-selective with respect to the liner 360, e.g., any of the isolator materials described herein. The liner 360 may be any material that can serve as an etch mask for etching the semiconductor material of the support structure 302 underneath, i.e., the liner 360 may include any material that is sufficiently etch-selective with respect to the semiconductor material of the support structure 302, e.g., a material that includes silicon and nitrogen (e.g., silicon nitride), or any other suitable material. Further variations to the loop trimming method described above are possible and are illustrated in
Although not specifically shown, the loop trimming method as illustrated in
The loop trimming method described above is not limited to arrangements of various components of the IC devices 350 as shown in
In the embodiment of
The angled elongated semiconductor structures 306 may serve as a foundation for forming transistors thereon (i.e., angled transistors), e.g., any of the transistors 110, 210, described above. Furthermore, other IC components may further be formed based on the angled elongated semiconductor structures 306, e.g., the memory cells 160, 260, described above. Various IC components (i.e., transistors, storage elements, etc.) formed based on the angled elongated semiconductor structures 306 will have terminals (e.g., the transistors will have gate terminals, drain terminals, and source terminals, the storage elements will have first and second electrode terminals, etc.) to which electrical connections will need to be made to electrically interconnect various IC components to one other and to other components of an IC device, as needed for a particular design. Because there are myriad of ways how different IC components such as transistors and storage elements may be implemented based on the angled elongated semiconductor structures 306 of the IC device 400A, details of these components are not shown in
Only one of the vias 402 are labeled in
In order to electrically interconnect the IC components based on the angled elongated semiconductor structures 306 of the IC device 400B, the vias 402 need to be coupled to a regular array of vias that could be stacked above them. As used herein, an array of vias is described as “regular” if the vias of the array are arranged in columns and rows where the vias are aligned both in their rows and in their columns. Vias in a given row may be described as “aligned” if the vias of that row may be aligned along a single horizontal line (in the plane of the drawings of
Ideally, all of the vias 408 would have the largest overlap with the respective vias 402, as greater overlap means lower contact resistance at the interface between a via 402 and a via 408 stacked on top of the via 402. However, as described above, the vias 408 have to be in a regular array, whereas, due to the nature of the angled orientation of the elongated semiconductor structures 306, the vias 402 are not in a regular array. Therefore, the process of arranging the vias 408 on top of the vias 402 may begin by selecting one terminal for which the overlap will be maximized, and then the remainder of the vias 408 will be aligned with respect to the via 408 of the selected terminal, since all of the vias 408 are in a regular array and, therefore, location of one of them dictates the location of the others. As shown in
Inventors of the present disclosure realized that, when the above-described approach to staggered via formation is implemented, the misalignment between a via 408 and a corresponding via 402 underneath the via 408 increases in all directions starting from the selected terminal for which the alignment was optimized. In other words, the misalignment increases in a radially outward direction (i.e., starting from a certain central point and increasing in all directions from that point). Such radial outward expansion of the misalignment can be seen in
The selected terminal for which the overlap between the vias 402 and 408 is maximized does not have to be substantially in the center of an array of terminals.
In some implementations, there may come a point where the misalignment between the vias 402 and 408 becomes too large and no effective contact can be made between the vias 402 and 408, e.g., as is shown with the great misalignment between the vias 402 and 408 of the terminal 47 in
It should be noted that while the vias 402 and 408 are shown in
Any of the angled transistors described herein (e.g., as described with reference to
The IC devices with angled transistors disclosed herein may be included in any suitable electronic device.
The package substrate 2252 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face 2272 and the face 2274, or between different locations on the face 2272, and/or between different locations on the face 2274.
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein (e.g., may include any of the embodiments of the IC devices with angled transistors as described herein). In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of the dies 2256 may be memory dies (e.g., high-bandwidth memory), including embedded memory dies as described herein. In some embodiments, any of the dies 2256 may include one or more IC devices with angled transistors, e.g., as discussed above; in some embodiments, at least some of the dies 2256 may not include any IC devices with angled transistors.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin transfer torque MRAM.
In some embodiments, the computing device 2400 may include a communication chip 2406 (e.g., one or more communication chips). For example, the communication chip 2406 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2406 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 1402.16 standards. The communication chip 2406 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2406 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2406 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2406 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2408 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2406 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2406 may include multiple communication chips. For instance, a first communication chip 2406 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2406 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2406 may be dedicated to wireless communications, and a second communication chip 2406 may be dedicated to wired communications.
The computing device 2400 may include a battery/power circuitry 2410. The battery/power circuitry 2410 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2412 (or corresponding interface circuitry, as discussed above). The display device 2412 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2414 (or corresponding interface circuitry, as discussed above). The audio output device 2414 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2416 (or corresponding interface circuitry, as discussed above). The audio input device 2416 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include an other output device 2418 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2418 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may include a GPS device 2422 (or corresponding interface circuitry, as discussed above). The GPS device 2422 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include a security interface device 2424. The security interface device 2424 may include any device that provides security features for the computing device 2400 or for any individual components therein (e.g., for the processing device 2402 or for the memory 2404). Examples of security features may include authorization, access to digital certificates, access to items in keychains, etc. Examples of the security interface device 2424 may include a software firewall, a hardware firewall, an antivirus, a content filtering device, or an intrusion detection device.
In some embodiments, the computing device 2400 may include a temperature detection device 2426 and a temperature regulation device 2428.
The temperature detection device 2426 may include any device capable of determining temperatures of the computing device 2400 or of any individual components therein (e.g., temperatures of the processing device 2402 or of the memory 2404). In various embodiments, the temperature detection device 2426 may be configured to determine temperatures of an object (e.g., the computing device 2400, components of the computing device 2400, devices coupled to the computing device, etc.), temperatures of an environment (e.g., a data center that includes, is controlled by, or otherwise associated with the computing device 2400), and so on. The temperature detection device 2426 may include one or more temperature sensors. Different temperature sensors of the temperature detection device 2426 may have different locations within and around the computing device 2400. A temperature sensor may generate data (e.g., digital data) representing detected temperatures and provide the data to another device, e.g., to the temperature regulation device 2428, the processing device 2402, the memory 2404, etc. In some embodiments, a temperature sensor of the temperature detection device 2426 may be turned on or off, e.g., by the processing device 2402 or an external system. The temperature sensor detects temperatures when it is on and does not detect temperatures when it is off. In other embodiments, a temperature sensor of the temperature detection device 2426 may detect temperatures continuously and automatically or detect temperatures at predefined times or at times triggered by an event associated with the computing device 2400 or any components therein.
The temperature regulation device 2428 may include any device configured to change (e.g., decrease) temperatures, e.g., based on one or more target temperatures and/or based on temperature measurements performed by the temperature detection device 2426. A target temperature may be a preferred temperature. A target temperature may depend on a setting in which the computing device 2400 operates. In some embodiments, the target temperature may be 200 Kelvin degrees or lower. In some embodiments, the target temperature may be 20 Kelvin degrees or lower, or 5 Kelvin degrees or lower. Target temperatures for different objects and different environments of, or associated with, the computing device 2400 can be different. In some embodiments, cooling provided by the temperature regulation device 2428 may be a multi-stage process with temperatures ranging from room temperature to 4K or lower.
In some embodiments, the temperature regulation device 2428 may include one or more cooling devices. Different cooling device may have different locations within and around the computing device 2400. A cooling device of the temperature regulation device 2428 may be associated with one or more temperature sensors of the temperature detection device 2426 and may be configured to operate based on temperatures detected the temperature sensors. For instance, a cooling device may be configured to determine whether a detected ambient temperature is above the target temperature or whether the detected ambient temperature is higher than the target temperature by a predetermined value or determine whether any other temperature-related condition associated with the temperature of the computing device 2400 is satisfied. In response to determining that one or more temperature-related condition associated with the temperature of the computing device 2400 are satisfied (e.g., in response to determining that the detected ambient temperature is above the target temperature), a cooling device may trigger its cooling mechanism and start to decrease the ambient temperature. Otherwise, the cooling device does not trigger any cooling. A cooling device of the temperature regulation device 2428 may operate with various cooling mechanisms, such as evaporation cooling, radiation cooling, conduction cooling, convection cooling, other cooling mechanisms, or any combination thereof. A cooling device of the temperature regulation device 2428 may include a cooling agent, such as a water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature regulation device 2428 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. In some embodiments, the temperature regulation device 2428 or any portions thereof (e.g., one or more of the individual cooling devices) may be connected to the computing device 2400 in close proximity (e.g., less than about 1 meter) or may be provided in a separate enclosure where a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) may reside.
By maintaining the target temperatures, the energy consumption of the computing device 2400 (or components thereof) can be reduced, while the computing efficiency may be improved. For example, when the computing device 2400 (or components thereof) operates at lower temperatures, energy dissipation (e.g., heat dissipation) may be reduced. Further, energy consumed by semiconductor components (e.g., energy needed for switching transistors of any of the components of the computing device 2400) can also be reduced. Various semiconductor materials may have lower resistivity and/or higher mobility at lower temperatures. That way, the electrical current per unit supply voltage may be increased by lowering temperatures. Conversely, for the same current that would be needed, the supply voltage may be lowered by lowering temperatures. As energy correlates to the supply voltage, the energy consumption of the semiconductor components may lower too. In some implementations, the energy savings due to reducing heat dissipation and reducing energy consumed by semiconductor components of the computing device or components thereof may outweigh (sometimes significantly outweigh) the costs associated with energy needed for cooling.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
A number of components are illustrated in
Additionally, in various embodiments, the processing device 2500 may not include one or more of the components illustrated in
The processing device 2500 may include logic circuitry 2502 (e.g., one or more circuits configured to implement logic/compute functionality). Examples of such circuits include ICs implementing one or more of input/output (I/O) functions, arithmetic operations, pipelining of data, etc.
In some embodiments, the logic circuitry 2502 may include one or more circuits responsible for read/write operations with respect to the data stored in the memory 2504. To that end, the logic circuitry 2502 may include one or more I/O ICs configured to control access to data stored in the memory 2504.
In some embodiments, the logic circuitry 2502 may include one or more high-performance compute dies, configured to perform various operations with respect to data stored in the memory 2504 (e.g., arithmetic and logic operations, pipelining of data from one or more memory dies of the memory 2504, and possibly also data from external devices/chips). In some embodiments, the logic circuitry 2502 may be configured to only control I/O access to data but not perform any operations on the data. In some embodiments, the logic circuitry 2502 may implement ICs configured to implement I/O control of data stored in the memory 2504, assemble data from the memory 2504 for transport (e.g., transport over a central bus) to devices/chips that are either internal or external to the processing device 2500, etc. In some embodiments, the logic circuitry 2502 may not be configured to perform any operations on the data besides I/O and assembling for transport to the memory 2504.
The processing device 2500 may include a memory 2504, which may include one or more ICs configure to implement memory circuitry (e.g., ICs implementing one or more of memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In some embodiments, the memory 2504 may be implemented substantially as described above with reference to the memory 2404 (
In some embodiments, the memory 2504 may include a flat memory (also sometimes referred to as a “flat hierarchy memory” or a “linear memory”) and, therefore, may also be referred to as a “basin memory.” As known in the art, a flat memory or a linear memory refers to a memory addressing paradigm in which memory may appear to the program as a single contiguous address space, where a processor can directly and linearly address all of the available memory locations without having to resort to memory segmentation or paging schemes. Thus, the memory implemented in the memory 2504 may be a memory that is not divided into hierarchical layer or levels in terms of access of its data.
In some embodiments, the memory 2504 may include a hierarchical memory. In this context, hierarchical memory refers to the concept of computer architecture where computer storage is separated into a hierarchy based on features of memory such as response time, complexity, capacity, performance, and controlling technology. Designing for high performance may require considering the restrictions of the memory hierarchy, i.e., the size and capabilities of each component. With hierarchical memory, each of the various memory components can be viewed as part of a hierarchy of memories (m1, m2, . . . , mn) in which each member mi is typically smaller and faster than the next highest member mi+1 of the hierarchy. To limit waiting by higher levels, a lower level of a hierarchical memory structure may respond by filling a buffer and then signaling for activating the transfer. For example, in some embodiments, the hierarchical memory implemented in the memory 2504 may be separated into four major storage levels: 1) internal storage (e.g., processor registers and cache), 2) main memory (e.g., the system RAM and controller cards), and 3) on-line mass storage (e.g., secondary storage), and 4) off-line bulk storage (e.g., tertiary, and off-line storage). However, as the number of levels in the memory hierarchy and the performance at each level has increased over time and is likely to continue to increase in the future, this example hierarchical division provides only one non-limiting example of how the memory 2504 may be arranged.
The processing device 2500 may include a communication device 2506, which may be implemented substantially as described above with reference to the communication chip 2406 (
The processing device 2500 may include interconnects 2508, which may include any element or device that includes an electrically conductive material for providing electrical connectivity to one or more components of, or associated with, a processing device 2500 or/and between various such components. Examples of the interconnects 2508 include conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”), metallization stacks, redistribution layers, metal-insulator-metal (MIM) structures, etc.
The processing device 2500 may include a temperature detection device 2510 which may be implemented substantially as described above with reference to the temperature detection device 2426 of
The processing device 2500 may include a temperature regulation device 2512 which may be implemented substantially as described above with reference to the temperature regulation device 2428 of
The processing device 2500 may include a battery/power circuitry 2514 which may be implemented substantially as described above with reference to the battery/power circuitry 2410 of
The processing device 2500 may include a hardware security device 2516 which may be implemented substantially as described above with reference to the security interface device 2424 of
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Unless specified otherwise, in various embodiments, features described with respect to one of the drawings may be combined with those described with respect to other drawings.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example A1 provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a first transistor provided over the support structure; and a second transistor provided over the support structure, where each of the second transistor and the first transistor includes a source region, a drain region, and a channel region spatially between the source region and the drain region, where a shortest line extending between the source region and the drain region of the first transistor is substantially parallel to an edge (e.g., at least one of the edges) of the support structure, and where a shortest line extending between the source region and the drain region of the second transistor is at an angle between 10 degrees and 80 degrees with respect to the edge of the support structure. The edge of the support structure may be, e.g., an edge of one of the opposing front and back faces of the support structure.
Example A2 provides the IC device according to example A1, where the support structure has a first face and an opposing second face.
Example A3 provides the IC device according to example A2, where the first transistor is provided over a first region of the first face of the support structure, and the second transistor is provided over a second region, not overlapping with the first region, of the first face of the support structure (i.e., both transistors are provided over the same face, or on the same side, of the support structure). In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on the same face of the support structure so that channel regions of these transistors include the semiconductor material.
Example A4 provides the IC device according to example A2, where the first transistor is provided over the first face of the support structure, and the second transistor is provided over the second face of the support structure. In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface of the first face and a surface of the second face that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on different faces of the support structure so that channel regions of these transistors include the semiconductor material.
Example A5 provides the IC device according to example A4, where a projection of the second transistor onto the support structure fully overlaps with or is within a projection of the first transistor onto the support structure or the projection of the first transistor onto the support structure fully overlaps with or is within the projection of the second transistor onto the support structure.
Example A6 provides the IC device according to example A4, where a projection of the second transistor onto the support structure is offset with respect to (e.g., does not overlap, or overlaps by less than about 75%) a projection of the first transistor onto the support structure.
Example A7 provides the IC device according to example A2, where the second transistor is one of a plurality of second transistors provided over the first face of the support structure, and the first transistor is nestled among the plurality of second transistors.
Example A8 provides the IC device according to example A2, where the first transistor is one of a plurality of first transistors provided over the first face of the support structure, and the second transistor is nestled among the plurality of first transistors.
Example A9 provides the IC device according to any one of examples A1-A8, where the support structure is a substrate that includes a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.
Example A10 provides the IC device according to example A1, where the support structure has a first face and an opposing second face, the first transistor is in a first layer over the first face of the support structure, the second transistor is in a second layer over the first face of the support structure (i.e., the first and second layers are over the same face of the support structure and are closer to that, first, face of the support structure than to the other, second, face of the support structure), and the IC device further includes a bonding layer between the first layer and the second layer.
Example A11 provides the IC device according to example A10, where the bonding layer includes a bonding material that includes an etch-stop material including silicon, nitrogen, and carbon, where an atomic percentage of each of silicon, nitrogen, and carbon within the etch-stop material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, indicating that these elements are added deliberately, as opposed to being accidental impurities which are typically in concentration below about 0.1%.
Example A12 provides the IC device according to any one of examples A10-A11, where the second layer is closer to the first face of the support structure than the first layer.
Example A13 provides the IC device according to example A12, further including a metallization stack, where the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization stack on top of the first layer, where the first IC die is then bonded, face down, to the front of a second IC die that includes the second layer).
Example A14 provides the IC device according to example A13, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.
Example A15 provides the IC device according to example A12, further including a metallization stack, where the first layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization stack on top of the first layer, where the first IC die is then bonded, backside down, to the front of a second IC die that includes the second layer).
Example A16 provides the IC device according to example A15, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the first layer.
Example A17 provides the IC device according to any one of examples A10-A11, where the first layer is closer to the first face of the support structure than the second layer.
Example A18 provides the IC device according to example A17, further including a metallization stack, where the metallization stack is between the bonding layer and the second layer, and the bonding layer is between the metallization stack and the first layer (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization stack on top of the second layer, where the second IC die is then bonded, face down, to the front of a first IC die that includes the first layer).
Example A19 provides the IC device according to example A18, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.
Example A20 provides the IC device according to example A17, further including a metallization stack, where the second layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization layer on top of the second layer, where the second IC die is then bonded, backside down, to the front of a first IC die that includes the first layer).
Example A21 provides the IC device according to example A20, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the second layer.
Example B1 provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); and a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided over the support structure, the plurality of angled structures including at least a first angled structure (e.g., 306-1) and a second angled structure (e.g., 306-2), where each of the angled structures includes a first end (e.g., 328-1), a second end (e.g., 328-2) opposite the first end, and a longitudinal axis (e.g., 320) extending between the first end and the second end, where the longitudinal axis of each of the angled structures is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may be, e.g., an edge of one of the two opposing faces of the support structure), and where the longitudinal axis of the first angled structure and the longitudinal axis of the second angled structure is a shared longitudinal axis.
Example B2 provides the IC device according to example B1, where the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and each of a projection of the first end of the first angled structure onto a plane parallel to the support structure and a projection of the second end of the second angled structure onto the plane is a straight line.
Example B3 provides the IC device according to example B2, where the straight line of the projection of the first end of the first angled structure onto the plane is parallel to the straight line of the projection of the second end of the second angled structure onto the plane.
Example B4 provides the IC device according to any one of examples B2-B3, where at least one (e.g., all) of the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is substantially parallel to the edge of the support structure.
Example B5 provides the IC device according to any one of examples B2-B3, where at least one of the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is at an angle between 10 degrees and 80 degrees with respect to the edge of the support structure.
Example B6 provides the IC device according to example B5, where at least one of a projection of the second end of the first angled structure onto the plane and a projection of the first end of the second angled structure onto the plane is substantially parallel to the edge of the support structure.
Example B7 provides the IC device according to any one of examples B1-B6, where the shared longitudinal axis is a first shared longitudinal axis, the plurality of angled structures further includes a third angled structure (e.g., 306-3) and a fourth angled structure (e.g., 306-4), the longitudinal axis of the third angled structure and the longitudinal axis of the fourth angled structure is a second shared longitudinal axis, and the first shared longitudinal axis (e.g., 320-1) and the second shared longitudinal axis (e.g., 320-2) are substantially parallel and at a distance to one another (i.e., they do not overlap or coincide).
Example B8 provides the IC device according to example B7, where the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), where the first end of the third angled structure is opposite the second end of the fourth angled structure (i.e., the first end of the third angled structure is closer to the second end of the fourth angled structure than the second end of the third angled structure, and the second end of the fourth angled structure is closer to the first end of the third angled structure than the first end of the fourth angled structure), and where each of a projection of the first end of the first angled structure onto a plane parallel to the support structure, a projection of the second end of the second angled structure onto the plane, a projection of the first end of the third angled structure onto the plane, and a projection of the second end of the fourth angled structure onto the plane is a straight line.
Example B9 provides the IC device according to example B8, where the straight line of the projection of the first end of the first angled structure onto the plane is parallel to the straight line of the projection of the second end of the second angled structure onto the plane, and the straight line of the projection of the first end of the third angled structure onto the plane is parallel to the straight line of the projection of the second end of the fourth angled structure onto the plane.
Example B10 provides the IC device according to any one of examples B8-B9, where at least one (e.g., all) of the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is substantially parallel to the edge of the support structure, and at least one (e.g., all) of the straight line of the projection of the first end of the third angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane is substantially parallel to the edge of the support structure.
Example B11 provides the IC device according to any one of examples B8-B10, where the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the first end of the third angled structure onto the plane are in different planes perpendicular to the support structure.
Example B12 provides the IC device according to example B11, where the straight line of the projection of the second end of the second angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane are in different planes perpendicular to the support structure.
Example B13 provides the IC device according to any one of examples B8-B12, where a distance between the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is different from a distance between the straight line of the projection of the first end of the third angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane.
Example B14 provides the IC device according to any one of examples B8-B10, where the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the first end of the third angled structure onto the plane are in a single first plane perpendicular to the support structure, and the straight line of the projection of the second end of the second angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane are in a single second plane perpendicular to the support structure.
Example B15 provides the IC device according to any one of examples B8-B10 or B14, where a distance between the straight line of the projection of the first end of the first angled structure onto the plane and the straight line of the projection of the second end of the second angled structure onto the plane is the same as a distance between the straight line of the projection of the first end of the third angled structure onto the plane and the straight line of the projection of the second end of the fourth angled structure onto the plane.
Example B16 provides the IC device according to example B1, where the first end of the first angled structure is opposite the second end of the second angled structure (i.e., the first end of the first angled structure is closer to the second end of the second angled structure than the second end of the first angled structure, and the second end of the second angled structure is closer to the first end of the first angled structure than the first end of the second angled structure), and where each of a projection of the first end of the first angled structure onto a plane parallel to the support structure and a projection of the second end of the second angled structure onto the plane is a curved line.
Example B17 provides the IC device according to example B16, where the curved line of the projection of the first end of the first angled structure onto the plane and the curved line of the projection of the second end of the second angled structure onto the plane are parts of an ellipse or an oval.
Example B18 provides the IC device according to any one of examples B1-B17, where the angled structures include a semiconductor material.
Example B19 provides the IC device according to any one of examples B1-B18, where one or more of the angled structures are fins of one or more semiconductor materials, the fins extending away from a base (where the base may be a part of the support structure or may be between the support structure and the fins).
Example B20 provides the IC device according to any one of examples B1-B19, where one or more of the angled structures are nanoribbons of one or more semiconductor materials.
Example B21 provides the IC device according to any one of examples B1-B20, further including a transistor provided over the support structure, where the transistor includes a source region, a drain region, and a channel region spatially between the source region and the drain region, where a shortest line extending between the source region and the drain region of the transistor is the shared longitudinal axis, and where the channel region of the transistor includes a semiconductor material of the first angled structure (i.e., the transistor is formed based on the first angled structure).
Example B22 provides the IC device according to example B21, further including a storage element coupled to the transistor.
Example B23 provides the IC device according to example B22, where the storage element is coupled to the source region or the drain region of the transistor.
Example B24 provides the IC device according to any one of examples B22-B23, where the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material.
Example B25 provides the IC device according to any one of examples B21-B24, where the transistor is a first transistor, the IC device further includes a second transistor provided over the support structure, and a shortest line extending between a source region of the second transistor and a drain region of the second transistor is substantially parallel to the edge of the support structure.
Example B26 provides the IC device according to example B25, where the support structure has a first face and an opposing second face.
Example B27 provides the IC device according to example B26, where the first transistor is provided over a first region of the first face of the support structure, and the second transistor is provided over a second region, not overlapping with the first region, of the first face of the support structure (i.e., both the non-angled and the second transistors are provided over the same face, or on the same side, of the support structure). In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on the same face of the support structure so that channel regions of these transistors include the semiconductor material.
Example B28 provides the IC device according to example B26, where the first transistor is provided over the first face of the support structure, and the second transistor is provided over the second face of the support structure. In some embodiments, the support structure may be a substrate of a semiconductor material or may be a substrate having a surface of the first face and a surface of the second face that includes a layer of a semiconductor material, and the non-angled and second transistors may be monolithically formed on different faces of the support structure so that channel regions of these transistors include the semiconductor material.
Example B29 provides the IC device according to example B28, where a projection of the second transistor onto the support structure fully overlaps with or is within a projection of the first transistor onto the support structure or the projection of the first transistor onto the support structure fully overlaps with or is within the projection of the second transistor onto the support structure.
Example B30 provides the IC device according to example B28, where a projection of the second transistor onto the support structure is offset with respect to (e.g., does not overlap, or overlaps by less than about 75%) a projection of the first transistor onto the support structure.
Example B31 provides the IC device according to example B26, where the second transistor is one of a plurality of second transistors provided over the first face of the support structure, and the first transistor is nestled among the plurality of second transistors.
Example B32 provides the IC device according to example B26, where the first transistor is one of a plurality of first transistors provided over the first face of the support structure, and the second transistor is nestled among the plurality of first transistors.
Example B33 provides the IC device according to any one of examples B25-B32, where the support structure is a substrate that includes a semiconductor material, the channel region of the first transistor includes a first portion of the semiconductor material, and the channel region of the second transistor includes a second portion of the semiconductor material.
Example B34 provides the IC device according to example B25, where the support structure has a first face and an opposing second face, the first transistor is in a first layer over the first face of the support structure, the second transistor is in a second layer over the first face of the support structure (i.e., the first and second layers are over the same face of the support structure and are closer to that, first, face of the support structure than to the other, second, face of the support structure), and the IC device further includes a bonding layer between the first layer and the second layer.
Example B35 provides the IC device according to example B34, where the bonding layer includes a bonding material that includes an etch-stop material including silicon, nitrogen, and carbon, where an atomic percentage of each of silicon, nitrogen, and carbon within the etch-stop material is at least about 1%, e.g., at least about 5%, e.g., between about 1% and 50%, indicating that these elements are added deliberately, as opposed to being accidental impurities which are typically in concentration below about 0.1%.
Example B36 provides the IC device according to any one of examples B34-B35, where the second layer is closer to the first face of the support structure than the first layer.
Example B37 provides the IC device according to example B36, further including a metallization stack, where the metallization stack is between the bonding layer and the first layer, and the bonding layer is between the metallization stack and the second layer (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization layer on top of the first layer, where the first IC die is then bonded, face down, to the front of a second IC die that includes the second layer).
Example B38 provides the IC device according to example B37, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.
Example B39 provides the IC device according to example B36, further including a metallization stack, where the first layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a first IC die that includes the first layer and the metallization layer on top of the first layer, where the first IC die is then bonded, backside down, to the front of a second IC die that includes the second layer).
Example B40 provides the IC device according to example B39, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the second layer and the bonding layer, and the bonding layer is between the redistribution layer and the first layer.
Example B41 provides the IC device according to any one of examples B34-B35, where the first layer is closer to the first face of the support structure than the second layer.
Example B42 provides the IC device according to example B41, further including a metallization stack, where the metallization stack is between the bonding layer and the second layer, and the bonding layer is between the metallization stack and the first layer (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization layer on top of the second layer, where the second IC die is then bonded, face down, to the front of a first IC die that includes the first layer).
Example B43 provides the IC device according to example B42, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the metallization stack.
Example B44 provides the IC device according to example B41, further including a metallization stack, where the second layer is between the bonding layer and the metallization stack (i.e., the metallization stack is a part of a second IC die that includes the second layer and the metallization layer on top of the second layer, where the second IC die is then bonded, backside down, to the front of a first IC die that includes the first layer).
Example B45 provides the IC device according to example B44, further including a redistribution layer having a plurality of interconnects configured to provide electrical connectivity between the first transistor and the first transistor, where the redistribution layer is between the first layer and the bonding layer, and the bonding layer is between the redistribution layer and the second layer.
Example C1 provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); an elongated structure (e.g., a fin or a nanoribbon) of a semiconductor material provided over the support structure; and a further structure of the semiconductor material (i.e., the same material as the elongated structure), proximate to the elongated structure, where a projection of the elongated structure on the support structure is substantially a rectangle, and a projection of the further structure on the support structure is a curve.
Example C2 provides the IC device according to example C1, where the projection of the further structure on the support structure has a U-shape.
Example C3 provides the IC device according to any one of examples C1-C2, where the rectangle has a first dimension in a first direction and a second dimension in a second direction, the first direction is perpendicular to the second direction, the first dimension greater than the second dimension, and the curve has a portion extending along the first direction.
Example C4 provides the IC device according to example C3, where a line along the first direction in the rectangle overlaps with a line along the first direction in the portion of the curve.
Example C5 provides the IC device according to any one of examples C3-C4, where the first direction is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may be, e.g., an edge of one of the two opposing faces of the support structure).
Example C6 provides the IC device according to any one of examples C3-C5, where a dimension of the portion of the curve extending along the first direction is less than 10% of the first dimension of the rectangle.
Example C7 provides the IC device according to any one of examples C1-C6, where a distance between the elongated structure and the further structure is between about 3 nanometers and 1000 nanometers, e.g., between about 5 nanometers and 100 nanometers, or between about 10 nanometers and 75 nanometers.
Example C8 provides the IC device according to any one of examples C1-C7, where the elongated structure is a fin extending away from the support structure, and the further structure is a curved structure extending away from the support structure.
Example C9 provides the IC device according to example C8, where a height of the fin is substantially equal to a height of the curved structure.
Example C10 provides the IC device according to any one of examples C1-C7, where the elongated structure is a nanoribbon extending parallel to the support structure, and the further structure is a curved structure extending parallel to the support structure.
Example C11 provides the IC device according to example C10, further including an insulator material between the nanoribbon and the support structure and between the curved structure and the support structure.
Example C12 provides the IC device according to any one of examples C1-C11, where a distance from the support structure to a surface of the elongated structure that is farthest away from the support structure is substantially equal to a distance from the support structure to a surface of the further structure that is farthest away from the support structure.
Example C13 provides the IC device according to any one of examples C1-C12, further including an insulator material between the elongated structure and the further structure.
Example C14 provides the IC device according to any one of examples C1-C13, where the further structure is not electrically connected to any other elements or components of the IC device.
Example C15 provides the IC device according to any one of examples C1-C14, where the further structure is enclosed by an insulator material on all sides (i.e., the further structure is not electrically connected to anything in the IC device).
Example D1 provides an IC device that includes a support structure (e.g., a die, a substrate, a carrier substrate, etc.); a plurality of angled structures (e.g., angled elongated semiconductor structures 306) provided over the support structure, where an individual angled structure of the plurality of angled structures includes a semiconductor material and is an elongated structure having a longitudinal axis that is substantially parallel to the support structure and is at an angle between 10 degrees and 80 degrees with respect to an edge of the support structure (the edge of the support structure may be, e.g., an edge of one of the two opposing faces of the support structure); a plurality of IC components based on the plurality of angled structures, the plurality of IC components having a plurality of terminals; and an array of stacked via pairs, including a first stacked via pair, a second stacked via pair, and a third stacked via pair, each stacked via pair of the array including a first via electrically coupled to a different one of the terminals, and a second via stacked above and electrically coupled to the first via, where an overlap between the first via and the second via for the first stacked via pair is larger than the overlap for the second stacked via pair and the overlap for the third stacked via pair, and where the second stacked via pair and the third stacked via pair are on opposite sides of the first stacked via pair.
Example D2 provides the IC device according to example D1, where the overlap for the first stacked via pair is largest from all stacked via pairs of the array.
Example D3 provides the IC device according to any one of examples D1-D2, where the overlap decreases in a radially outward manner starting from the first stacked via pair.
Example D4 provides the IC device according to any one of examples D1-D3, where the overlap for the first stacked via pair is larger than the overlap of each stacked via pair that is a nearest-neighbor to the first stacked via pair.
Example D5 provides the IC device according to example D4, where the overlap for at least one stacked via pair that is the nearest-neighbor to the first stacked via pair is larger than the overlap for at least one stacked via pair that is a second-nearest-neighbor to the first stacked via pair.
Example D6 provides the IC device according to any one of examples D1-D5, where the overlap for at least two stacked via pairs that are nearest-neighbors to the first stacked via pair is larger than the overlap for at least two stacked via pairs that are second-nearest-neighbors to the first stacked via pair.
Example D7 provides the IC device according to any one of examples D1-D6, where, for the each stacked via pair, the first via is between the one of the terminals and the second via.
Example D8 provides the IC device according to any one of examples D1-D7, where the second vias of the array of stacked via pairs are arranged in rows and columns, for each of the rows, distances between different pairs of nearest-neighbor second vias of the row are substantially same, and, for each of the columns, distances between different pairs of nearest-neighbor second vias of the column are substantially same.
Example D9 provides the IC device according to example D8, where, for each of the rows, second vias of the row are aligned along a single line, and, for each of the columns, second vias of the column are aligned along a single line.
Example D10 provides the IC device according to any one of examples D1-D9, further including a plurality of non-angled structures (e.g., non-angled elongated semiconductor structures 304) provided over the array of stacked via pairs, where an individual non-angled structure of the plurality of non-angled structures includes a semiconductor material and is an elongated structure having a longitudinal axis that is substantially parallel to the support structure and is parallel or perpendicular with respect to the edge of the support structure (the same edge as in example 1);
and a plurality of further IC components based on the plurality of non-angled structures, the plurality of further IC components having a plurality of further terminals, where one more of the second vias of the array of stacked via pairs are electrically coupled to one of more of the further terminals.
Example E1 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a central processing unit.
Example E2 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a memory device, e.g., a high-bandwidth memory device.
Example E3 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device further includes a plurality of memory cells, each of the memory cells including a storage element.
Example E4 provides the IC device according to example E3, where the storage element is one of a capacitor, a magnetoresistive material, a ferroelectric material, or a resistance-changing material.
Example E5 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a logic circuit.
Example E6 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of input/output circuitry.
Example E7 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of an FPGA transceiver.
Example E8 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of an FPGA logic.
Example E9 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a power delivery circuitry.
Example E10 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of a III-V amplifier.
Example E11 provides the IC device according to any one of the preceding examples A, B, C, or D, where the IC device includes or is a part of PCIE circuitry or DDR transfer circuitry.
Example E12 provides an IC package that includes an IC device according to any one of the preceding examples A, B, C, D, or E; and a further IC component, coupled to the IC die.
Example E13 provides the IC package according to example E12, where the further IC component includes one of a package substrate, an interposer, or a further IC die.
Example E14 provides a computing device that includes a carrier substrate and an IC device, coupled to the carrier substrate, where the IC device is an IC device according to any one of the preceding examples A, B, C, D, or E, or the IC device is included in the IC package according to any one of examples E12-E13.
Example E15 provides the computing device according to example E14, where the computing device is a wearable or handheld computing device.
Example E16 provides the computing device according to examples E14 or E15, where the computing device further includes one or more communication chips and an antenna.
Example E17 provides the computing device according to any one of examples E14-E16, where the carrier substrate is a motherboard.
Example E18 provides a method of manufacturing an IC device, the method including providing the IC device according to any one of the preceding examples.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2022/023022 | 4/1/2022 | WO |
