Takeo Yasuda

Person

Shiga, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Asymmetrical clock separation and stage delay optimization in singl...
- Patent number 12,294,369
- Issue date May 6, 2025
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synapse memory
- Patent number 12,198,039
- Issue date Jan 14, 2025
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias scheme for single-device synaptic element
- Patent number 12,124,946
- Issue date Oct 22, 2024
- International Business Machines Corporation
- Masatoshi Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance and area efficient synapse memory cell structure
- Patent number 11,809,982
- Issue date Nov 7, 2023
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transfer with continuous weighted PPM duration signal
- Patent number 11,789,857
- Issue date Oct 17, 2023
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias scheme for single-device synaptic element
- Patent number 11,741,353
- Issue date Aug 29, 2023
- International Business Machines Corporation
- Masatoshi Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synapse memory
- Patent number 11,586,882
- Issue date Feb 21, 2023
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synapse weight update compensation
- Patent number 11,475,946
- Issue date Oct 18, 2022
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synapse memory cell driver
- Patent number 11,321,608
- Issue date May 3, 2022
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems of neuron leaky integrate and fire circuits
- Patent number 11,308,390
- Issue date Apr 19, 2022
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Weight shifting for neuromorphic synapse array
- Patent number 11,188,815
- Issue date Nov 30, 2021
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NVM synaptic element with gradual reset capability
- Patent number 11,087,811
- Issue date Aug 10, 2021
- International Business Machines Corporation
- Akiyo Iwashina
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Timing sequence for digital STDP synapse and LIF neuron-based neuro...
- Patent number 11,003,984
- Issue date May 11, 2021
- Samsung Electronics Co., Ltd.
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LUT based synapse weight update scheme in STDP neuromorphic systems
- Patent number 10,891,543
- Issue date Jan 12, 2021
- Samsung Electronics Co., Ltd.
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digitial STDP synapse and LIF neuron-based neuromorphic system
- Patent number 10,762,419
- Issue date Sep 1, 2020
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LUT based neuron membrane potential update scheme in STDP neuromorp...
- Patent number 10,748,058
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Current mirror scheme for an integrating neuron circuit
- Patent number 10,671,911
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems of neuron leaky integrate and fire circuits
- Patent number 10,643,125
- Issue date May 5, 2020
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital STDP synapse and LIF neuron-based neuromorphic system
- Patent number 10,552,731
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell structure
- Patent number 10,446,231
- Issue date Oct 15, 2019
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell structure
- Patent number 10,297,321
- Issue date May 21, 2019
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell structure
- Patent number 10,090,047
- Issue date Oct 2, 2018
- International Business Machines Corporation
- Kohji Hosokawa
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed and low power circuit structure for barrel shifter
- Patent number 9,996,317
- Issue date Jun 12, 2018
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed and low power circuit structure for barrel shifter
- Patent number 9,501,260
- Issue date Nov 22, 2016
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-adjusting duty cycle tuner
- Patent number 9,484,894
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-adjusting duty cycle tuner
- Patent number 9,484,895
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed and low power circuit structure for barrel shifter
- Patent number 9,021,000
- Issue date Apr 28, 2015
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device
- Patent number 8,717,836
- Issue date May 6, 2014
- International Business Machines Corporation
- Takeo Yasuda
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 8,295,105
- Issue date Oct 23, 2012
- International Business Machines Corporation
- Takeo Yasuda
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for glitchless clock multiplexer optimized for synchronou...
- Patent number 8,086,989
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Eskinder Hailu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HANDLING SURGE OF CURRENT DUE TO A SUDDEN INCREASE IN OPERATION LOAD
- Publication number 20250112551
- Publication date Apr 3, 2025
- International Business Machines Corporation
- Takeo Yasuda
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
PERFORMANCE AND AREA EFFICIENT SYNAPSE MEMORY CELL STRUCTURE
- Publication number 20240020522
- Publication date Jan 18, 2024
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFECTIVE SYNCHRONOUS GATES FOR RAPID SINGLE FLUX QUANTUM LOGIC
- Publication number 20230351234
- Publication date Nov 2, 2023
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRICAL CLOCK SEPARATION AND STAGE DELAY OPTIMIZATION IN SINGL...
- Publication number 20230344432
- Publication date Oct 26, 2023
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS SCHEME FOR SINGLE-DEVICE SYNAPTIC ELEMENT
- Publication number 20230297821
- Publication date Sep 21, 2023
- International Business Machines Corporation
- Masatoshi Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNAPSE MEMORY
- Publication number 20230076654
- Publication date Mar 9, 2023
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TRANSFER WITH CONTINUOUS WEIGHTED PPM DURATION SIGNAL
- Publication number 20230046980
- Publication date Feb 16, 2023
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS SCHEME FOR SINGLE-DEVICE SYNAPTIC ELEMENT
- Publication number 20220180165
- Publication date Jun 9, 2022
- International Business Machines Corporation
- Masatoshi Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE AND AREA EFFICIENT SYNAPSE MEMORY CELL STRUCTURE
- Publication number 20210241086
- Publication date Aug 5, 2021
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNAPSE WEIGHT UPDATE COMPENSATION
- Publication number 20210225439
- Publication date Jul 22, 2021
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WEIGHT SHIFTING FOR NEUROMORPHIC SYNAPSE ARRAY
- Publication number 20200218963
- Publication date Jul 9, 2020
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS
- Publication number 20200026994
- Publication date Jan 23, 2020
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM
- Publication number 20190354845
- Publication date Nov 21, 2019
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNAPSE MEMORY
- Publication number 20190228292
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNAPSE MEMORY CELL DRIVER
- Publication number 20190228295
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL STRUCTURE
- Publication number 20190206490
- Publication date Jul 4, 2019
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL STRUCTURE
- Publication number 20180322920
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Kohji Hosokawa
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL STRUCTURE
- Publication number 20180130528
- Publication date May 10, 2018
- International Business Machines Corporation
- Kohji Hosokawa
- G11 - INFORMATION STORAGE
Information Patent Application
Timing Sequence for Digital STDP Synapse and LIF Neuron-based Neuro...
- Publication number 20170344885
- Publication date Nov 30, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS
- Publication number 20170255860
- Publication date Sep 7, 2017
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Current Mirror Scheme for An Integrating Neuron Circuit
- Publication number 20170243108
- Publication date Aug 24, 2017
- International Business Machines Corporation
- Mark B. Ritter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM
- Publication number 20170185890
- Publication date Jun 29, 2017
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LUT BASED SYNAPSE WEIGHT UPDATE SCHEME IN STDP NEUROMORPHIC SYSTEMS
- Publication number 20170185889
- Publication date Jun 29, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LUT BASED NEURON MEMBRANE POTENTIAL UPDATE SCHEME IN STDP NEUROMORP...
- Publication number 20170185891
- Publication date Jun 29, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSE GENERATOR WITH SWITCHED CAPACITORS
- Publication number 20170047911
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PULSE GENERATOR WITH SWITCHED CAPACITORS
- Publication number 20170047914
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Kohji Hosokawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER
- Publication number 20150149518
- Publication date May 28, 2015
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-ADJUSTING DUTY CYCLE TUNER
- Publication number 20140084979
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER
- Publication number 20140089363
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Takeo Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-ADJUSTING DUTY CYCLE TUNER
- Publication number 20140009197
- Publication date Jan 9, 2014
- International Business Machines Corporation
- Takeo Yasuda
- H03 - BASIC ELECTRONIC CIRCUITRY

Takeo Yasuda

Person

Patents Grantslast 30 patents

Asymmetrical clock separation and stage delay optimization in singl...

Synapse memory

Bias scheme for single-device synaptic element

Performance and area efficient synapse memory cell structure

Data transfer with continuous weighted PPM duration signal

Bias scheme for single-device synaptic element

Synapse memory

Synapse weight update compensation

Synapse memory cell driver

Methods and systems of neuron leaky integrate and fire circuits

Weight shifting for neuromorphic synapse array

NVM synaptic element with gradual reset capability

Timing sequence for digital STDP synapse and LIF neuron-based neuro...

LUT based synapse weight update scheme in STDP neuromorphic systems

Digitial STDP synapse and LIF neuron-based neuromorphic system

LUT based neuron membrane potential update scheme in STDP neuromorp...

Current mirror scheme for an integrating neuron circuit

Methods and systems of neuron leaky integrate and fire circuits

Digital STDP synapse and LIF neuron-based neuromorphic system

Memory cell structure

Memory cell structure

Memory cell structure

High speed and low power circuit structure for barrel shifter

High speed and low power circuit structure for barrel shifter

Self-adjusting duty cycle tuner

Self-adjusting duty cycle tuner

High speed and low power circuit structure for barrel shifter

Semiconductor memory device

Semiconductor memory device

Structure for glitchless clock multiplexer optimized for synchronou...

Patents Applicationslast 30 patents

HANDLING SURGE OF CURRENT DUE TO A SUDDEN INCREASE IN OPERATION LOAD

PERFORMANCE AND AREA EFFICIENT SYNAPSE MEMORY CELL STRUCTURE

EFFECTIVE SYNCHRONOUS GATES FOR RAPID SINGLE FLUX QUANTUM LOGIC

ASYMMETRICAL CLOCK SEPARATION AND STAGE DELAY OPTIMIZATION IN SINGL...

BIAS SCHEME FOR SINGLE-DEVICE SYNAPTIC ELEMENT

SYNAPSE MEMORY

DATA TRANSFER WITH CONTINUOUS WEIGHTED PPM DURATION SIGNAL

BIAS SCHEME FOR SINGLE-DEVICE SYNAPTIC ELEMENT

PERFORMANCE AND AREA EFFICIENT SYNAPSE MEMORY CELL STRUCTURE

SYNAPSE WEIGHT UPDATE COMPENSATION

WEIGHT SHIFTING FOR NEUROMORPHIC SYNAPSE ARRAY

METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS

DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM

SYNAPSE MEMORY

SYNAPSE MEMORY CELL DRIVER

MEMORY CELL STRUCTURE

MEMORY CELL STRUCTURE

MEMORY CELL STRUCTURE

Timing Sequence for Digital STDP Synapse and LIF Neuron-based Neuro...

METHODS AND SYSTEMS OF NEURON LEAKY INTEGRATE AND FIRE CIRCUITS

Current Mirror Scheme for An Integrating Neuron Circuit

DIGITIAL STDP SYNAPSE AND LIF NEURON-BASED NEUROMORPHIC SYSTEM

LUT BASED SYNAPSE WEIGHT UPDATE SCHEME IN STDP NEUROMORPHIC SYSTEMS

LUT BASED NEURON MEMBRANE POTENTIAL UPDATE SCHEME IN STDP NEUROMORP...

PULSE GENERATOR WITH SWITCHED CAPACITORS

PULSE GENERATOR WITH SWITCHED CAPACITORS

HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER

SELF-ADJUSTING DUTY CYCLE TUNER

HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER

SELF-ADJUSTING DUTY CYCLE TUNER