Takuya Ariki

Person

Yokohama, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Word line architecture for three dimensional NAND flash memory
- Patent number 11,177,277
- Issue date Nov 16, 2021
- SanDisk Technologies LLC
- Naoki Ookuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory plane structure for ultra-low read latency applications in n...
- Patent number 11,081,192
- Issue date Aug 3, 2021
- SanDiskTechnologies LLC.
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line decoder circuitry under a three-dimensional memory array
- Patent number 10,991,429
- Issue date Apr 27, 2021
- SanDisk Technologies LLC
- Hiroyuki Ogawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Differential dbus scheme for low-latency random read for NAND memories
- Patent number 10,984,874
- Issue date Apr 20, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Area effective erase voltage isolation in NAND memory
- Patent number 10,885,984
- Issue date Jan 5, 2021
- SanDisk Technologies LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory device containing bit line switches
- Patent number 10,854,619
- Issue date Dec 1, 2020
- SanDisk Technologies LLC
- Hardwell Chibvongodze
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory device containing bit line switches
- Patent number 10,734,080
- Issue date Aug 4, 2020
- SanDisk Technologies LLC
- Hardwell Chibvongodze
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line decoder circuitry under a three-dimensional memory array
- Patent number 10,720,213
- Issue date Jul 21, 2020
- SanDisk Technologies LLC
- Hiroyuki Ogawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line decoder circuitry under a three-dimensional memory array
- Patent number 9,721,663
- Issue date Aug 1, 2017
- SanDisk Technologies LLC
- Hiroyuki Ogawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Integration of word line switches with word line contact via struct...
- Patent number 9,595,535
- Issue date Mar 14, 2017
- SanDisk Technologies LLC
- Hiroyuki Ogawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Level shifter with negative voltage capability
- Patent number 8,395,434
- Issue date Mar 12, 2013
- SanDisk Technologies Inc.
- Qui Vi Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory and related voltage regulator
- Patent number 8,076,911
- Issue date Dec 13, 2011
- Samsung Electronics Co., Ltd.
- Takuya Ariki
- G05 - CONTROLLING REGULATING
Information Patent Grant
Discharge circuit
- Patent number 7,881,122
- Issue date Feb 1, 2011
- Samsung Electronics Co., Ltd.
- Takuya Ariki
- G11 - INFORMATION STORAGE
Information Patent Grant
Write voltage generating circuit and method
- Patent number 7,710,793
- Issue date May 4, 2010
- Samsung Electronics Co., Ltd.
- Yuichiro Nakagaki
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES
- Publication number 20210142858
- Publication date May 13, 2021
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY
- Publication number 20210134828
- Publication date May 6, 2021
- SANDISK TECHNOLOGIES LLC
- Naoki Ookuma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY PLANE STRUCTURE FOR ULTRA-LOW READ LATENCY APPLICATIONS IN N...
- Publication number 20210134375
- Publication date May 6, 2021
- SANDISK TECHNOLOGIES LLC
- Hiroki Yabe
- G11 - INFORMATION STORAGE
Information Patent Application
WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY
- Publication number 20200294599
- Publication date Sep 17, 2020
- SANDISK TECHNOLOGIES LLC
- Hiroyuki OGAWA
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BIT LINE SWITCHES
- Publication number 20200185397
- Publication date Jun 11, 2020
- SANDISK TECHNOLOGIES LLC
- Hardwell Chibvongodze
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BIT LINE SWITCHES
- Publication number 20200185039
- Publication date Jun 11, 2020
- SANDISK TECHNOLOGIES LLC
- Hardwell Chibvongodze
- G11 - INFORMATION STORAGE
Information Patent Application
Word Line Decoder Circuitry under a Three-Dimensional Memory Array
- Publication number 20190057741
- Publication date Feb 21, 2019
- SanDisk Technologies LLC
- Hiroyuki OGAWA
- G11 - INFORMATION STORAGE
Information Patent Application
WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY
- Publication number 20170243650
- Publication date Aug 24, 2017
- SANDISK TECHNOLOGIES INC.
- Hiroyuki OGAWA
- G11 - INFORMATION STORAGE
Information Patent Application
DISCHARGE CIRCUIT
- Publication number 20090179694
- Publication date Jul 16, 2009
- Samsung Electronics Co., Ltd.
- Takuya Ariki
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE VOLTAGE GENERATING CIRCUIT AND METHOD
- Publication number 20090046518
- Publication date Feb 19, 2009
- Samsung Electronics Co., Ltd.
- Yuichiro NAKAGAKI
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY AND RELATED VOLTAGE REGULATOR
- Publication number 20090001950
- Publication date Jan 1, 2009
- Samsung Electronics Co., Ltd.
- Takuya Ariki
- G05 - CONTROLLING REGULATING

Takuya Ariki

Person

Patents Grantslast 30 patents

Word line architecture for three dimensional NAND flash memory

Memory plane structure for ultra-low read latency applications in n...

Word line decoder circuitry under a three-dimensional memory array

Differential dbus scheme for low-latency random read for NAND memories

Area effective erase voltage isolation in NAND memory

Three-dimensional memory device containing bit line switches

Three-dimensional memory device containing bit line switches

Word line decoder circuitry under a three-dimensional memory array

Word line decoder circuitry under a three-dimensional memory array

Integration of word line switches with word line contact via struct...

Level shifter with negative voltage capability

Flash memory and related voltage regulator

Discharge circuit

Write voltage generating circuit and method

Patents Applicationslast 30 patents

DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES

WORD LINE ARCHITECTURE FOR THREE DIMENSIONAL NAND FLASH MEMORY

MEMORY PLANE STRUCTURE FOR ULTRA-LOW READ LATENCY APPLICATIONS IN N...

WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BIT LINE SWITCHES

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BIT LINE SWITCHES

Word Line Decoder Circuitry under a Three-Dimensional Memory Array

WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY

DISCHARGE CIRCUIT

WRITE VOLTAGE GENERATING CIRCUIT AND METHOD

FLASH MEMORY AND RELATED VOLTAGE REGULATOR